K4T1G164QE-HCF7

Manufacturer Part NumberK4T1G164QE-HCF7
ManufacturerSamsung
K4T1G164QE-HCF7 datasheet
 

Specifications of K4T1G164QE-HCF7

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24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the V
single-ended data strobe crossing V
IH/L
the single-ended data strobe crossing V
be monotonic between V
(DC)max and V
IL
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the V
single-ended data strobe crossing V
(AC) at the end of its transition for a rising signal, and from the input signal crossing at the V
IH/L
single-ended data strobe crossing V
IH/L
monotonic between V
(DC)max and V
IL
IH
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period
of tIS + 2 x tCK + tIH.
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respec-
tive clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup
and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is
present or not.
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec val-
ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these
parameters should be met whether clock jitter is present or not.
31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/
R)DQS/DQS) crossing.
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means:
For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications
are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set.
34. New units, ’tCK(avg)’ and ’nCK’, are introduced in DDR2-667 and DDR2-800. Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under
operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ’tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x
tCK(avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these
parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
Parameter
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
Cycle to cycle clock period jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles, n = 6 ... 10, inclusive
Cumulative error across n cycles, n = 11 ... 50, inclusive
Duty cycle jitter
(DC) at the start of its transition for a rising signal, and from the input signal crossing at the V
(DC) at the start of its transition for a falling signal applied to the device under test. The DQS signal must
IH/L
(DC)min.
IH
(AC) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
(DC)min.
DDR2-667
Symbol
Min
tJIT(per)
-125
tJIT(per,lck)
-100
tJIT(cc)
-250
tJIT(cc,lck)
-200
tERR(2per)
-175
tERR(3per)
-225
tERR(4per)
-250
tERR(5per)
-250
tERR(6-10per)
-350
tERR(11-50per)
-450
tJIT(duty)
-125
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DDR2 SDRAM
(AC) level to the
IH
IL
(DC) level to the
IH
(DC) level to the
IL
DDR2-800
units
Max
Min
Max
125
-100
100
ps
100
-80
80
ps
250
-200
200
ps
200
-160
160
ps
175
-150
150
ps
225
-175
175
ps
250
-200
200
ps
250
-200
200
ps
350
-300
300
ps
450
-450
450
ps
125
-100
100
ps
Rev. 1.1 December 2008
(AC) level to
Notes
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