ax88796 ASIX Electronics Corporation, ax88796 Datasheet
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ax88796 Summary of contents
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... The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802 ...
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... A IN ONNECTION 1.3 AX88796 ONNECTION 1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode .....................................................................................8 1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode ........................................................................................9 1.3.3 AX88796 Pin Connection Diagram for MC68K Mode ...................................................................................10 1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode...................................................................................11 2.0 SIGNAL DESCRIPTION........................................................................................................................................12 2.1 L CPU OCAL ...
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... APPENDIX A: APPLICATION NOTE 1...................................................................................................................67 A 25MH ........................................................................................................................................67 SING RYSTAL Z A 25MH ..................................................................................................................................67 SING SCILLATOR Z APPENDIX B: POWER CONSUMPTION REFERENCE DATA ..........................................................................68 ERRATA OF AX88796..................................................................................................................................................69 DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY.................................72 Date(M/D/Y)............................................................................................................................................................77 3-in-1 Local Bus Fast Ethernet Controller ...........................................................................................................................40 . .........................................................................................................................51 ..............................................................................................................51 ...........................................................................................................52 . .........................................................................................................52 ..........................................................................................53 ANAGEMENT FUNCTIONS ..............................................................................................................................54 ........................................................................................................................54 .............................................................................................................................55 3 ASIX ELECTRONICS CORPORATION ...
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... AX88796 LOCK IAGRAM AX88796 ONNECTION AX88796 ONNECTION AX88796 ONNECTION AX88796 ONNECTION AX88796 ONNECTION AX88796 ONNECTION ..........................................................................................................................................22 IG ECEIVE UFFER ING ...
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... The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802 ...
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... AX88796 L 1.3a AX88796 Pin Connection Diagram The AX88796 is housed in the 128-pin plastic light quad flat pack. Fig - 2 shows the AX88796 pin connection diagram. GPI[0]/LINK 103 VDD 104 VSS 105 GPI[1]/DPX 106 TX_CLK 107 TX_EN 108 TXD[0] 109 TXD[1] 110 TXD[2] ...
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... NC NC 122 /IOCS16 123 NC 124 NC 125 VDD 126 VSS 127 /CS 128 Fig - 3 AX88796 Pin Connection Diagram with SPP Port Option 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus Controller (With SPP Port VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] ...
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... NC NC 122 /IOCS16 123 NC 124 NC 125 VDD 126 VSS 127 /CS 128 Fig - 4 AX88796 Pin Connection Diagram for ISA Bus Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for ISA Bus I/ VSS 63 I_ACT 62 I_SPEED 61 I_LINK ...
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... NC NC 122 (for x86 Interface) NC 123 124 NC NC 125 VDD 126 VSS 127 /CS 128 Fig - 5 AX88796 Pin Connection Diagram for 80x86 Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] ...
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... NC NC 122 NC 123 (for 68K Interface) 124 NC NC 125 VDD 126 VSS 127 /CS 128 Fig - 6 AX88796 Pin Connection Diagram for MC68K Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] ...
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... NC NC 122 (for 8051 Interface) 123 NC NC 124 NC 125 VDD 126 VSS 127 /CS 128 Fig - 7 AX88796 Pin Connection Diagram for MCS-51 Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS I_ACT 62 I_SPEED 61 I_LINK 60 ...
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... DMA cycle. When negated (low), AX88796 an I/O slave device may respond to addresses and I/O command. PSEN : This signal is active low for 8051 program access. For I/O device, AX88796, this signal is active high to access the chip. This signal is for 8051 bus application only. 12 ...
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... AX88796 L 2.2 10/100Mbps Twisted-Pair Interface pins group SIGNAL TYPE PIN NO. TPI+ I TPI- I TPO+ O TPO- O REXT10 I REXT100 I REXTBS I Tab - 2 10/100Mbps Twisted-Pair Interfaces pins group 2.3 Built-in PHY LED indicator pins group SIGNAL TYPE PIN NO. I_ACT O or I_FULL/COL I_SPEED O I_LINK O Or I_LK/ACT Tab - 3 Built-in PHY LED indicator pins group ...
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... AX88796 L 2.4 EEPROM Signals Group SIGNAL TYPE PIN NO. EECS O EECK O/PD EEDI O EEDO I/PU Tab - 4 EEPROM bus interface signals group 2.5 MII interface signals group (Optional) SIGNAL TYPE PIN NO. RXD[3:0] I/PU 98 – 95 CRS I/PD RX_DV I/PD RX_ER (Omit) No Support Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK I/PU COL ...
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... AX88796 L 2.6 Standard Printer Port (SPP) Interface pins group (Optional) SIGNAL TYPE PIN NO. PD[7:5] I/O/PD 102 – 100 PD[4:0] I/O/ BUSY I/PU /ACK I/PU PE I/PU SLCT I/PU /ERR I/PU /SLCTIN O /INIT O /ATFD O /STRB O Tab - 6 Standard Printer Port Interface pins group 2.7 General Purpose I/O pins group Signal Name Type Pin No. GPI[2]/SPD ...
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... XTALIN, the crystal output pin should be left floating. 44 Clock Output : This clock is source from LCLK/XTALIN. 3 Reset : Reset is active high then place AX88796 into reset mode immediately. During the falling edge the AX88796 loads the power on setting data. CPU type selection: CPU[1] CPU[ ...
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... AX88796 L 73, 82 VSSA P 55, 68, 72, 75, 85, VDDM P VSSM P 77, 93 VDDPD P VSSPD P VDDO P VSSO P 86, 89, 90 Tab - 8 Miscellaneous pins group 2.9 Power on configuration setup signals cross reference table Signal Name Share with /SPP_SET MDC Tab - 9 Power on Configuration Setup Table 3-in-1 Local Bus Fast Ethernet Controller Power Supply for Analog Circuit: + Ground Power ...
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... AX88796 L 3.0 Memory and I/O Mapping There are three memories or I/O mapping used in AX88796. 1. EEPROM Memory Mapping 2. I/O Mapping 3. Local Memory Mapping 3.1 EEPROM Memory Mapping User can define by them and can access via I/O address offset 14H MII/EEPROM registers. The contants of EEPROM will not be loading to any registers automaticlly. ...
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... AX88796 L 4.0 Basic Operation 4.1 Receiver Filtering The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast destination addresses are filtered using a hashing algorithm ...
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... Filter bit array If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1''. This will cause the AX88796 to accept any multicast packet with the address Y. Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter logical address filteres if these addresses are chosen to map into unique locations in the multicast filter ...
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... AX88796 L Aggregate Address Filter function will be: Bro AND Logic AB /Bro /Mul AND Logic PRO /Bro Mul AND Logic AM Phy 3-in-1 Local Bus Fast Ethernet Controller OR Logic 21 ASIX ELECTRONICS CORPORATION AGG ...
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... Two eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define the physical boundaries of where the buffers reside. The AX88796 treats the list of buffers as a logical ring; whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address ...
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... Fig - 9 Receive Buffer Ring At Initialization BEGINNING OF RECEPTION When the first packet begins arriving the AX88796 and begins storing the packet at the location pointed to by the Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receive status corresponding to this packet. ...
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... Read the stored value of the TXP bit from step 1, above. If this value set the ``Resend'' variable and jump to step 6. If this value read the AX88796's Interrupt Status Register. If either the Packet Transmitted bit (PTX) or Transmit Error bit (TXE) is set set the ``Resend'' variable and jump to step 6 ...
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... Command Register. If the ``Resend'' variable is 0, nothing needs to bedone. END OF PACKET OPERATIONS At the end of the packet the AX88796 determines whether the received packet accepted or rejected. It either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store the packet. ...
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... RAM handshaking with system transfers loading the I/O data port. The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting the pins for ISA, 80186 or MC68K mode ...
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... AX88796 L Source Address 1 Source Address 3 Source Address 5 Type / Length 1 BOS = 0, WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode. D15 Destination Address 0 Destination Address 2 Destination Address 4 Source Address 0 Source Address 2 Source Address 4 Type / Length 0 BOS = 1, WTS = 1 in Data Configuration Register. ...
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... When initializing the AX88796 set: BNRY = PSTART CPR = PSTART + 1 Next_pkt = PSTART + 1 3. After a packet is DMAed from the Receive Buffer Ring, the Next Page Pointer (second byte in AX88796 receive packet buffer header) is used to update BNRY and next_pkt. Next_pkt = Next Page Pointer BNRY = Next Page Pointer - 1 If BNRY < ...
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... AX88796 L 3-in-1 Local Bus Fast Ethernet Controller D15 Next Packet Pointer Receive Byte Count 1 Destination Address 1 Destination Address 3 Destination Address 5 Source Address 1 Source Address 3 Source Address 5 Type / Length 1 Data 1 … BOS = 0, WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode. ...
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... AX88796 L 3-in-1 Local Bus Fast Ethernet Controller D7 Next Packet Pointer Receive Byte Count 0 Receive Byte Count 1 Destination Address 0 Destination Address 1 Destination Address 2 Destination Address 3 Destination Address 4 Destination Address 5 Source Address 0 Source Address 1 Source Address 2 Source Address 3 Source Address 4 Source Address 5 BOS = 0, WTS = 0 in Data Configuration Register. ...
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... Command Register. Writing 21H to the Command Register will stop the AX88796. 2. Wait for at least 1.5 ms. Since the AX88796 will complete any reception that is in progress necessary to time out for the maximum possible duration of an Ethernet reception. This action prevents buffer memory from written data through Local DMA Write ...
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... AX88796 L 5.0 Registers Operation 5.1 MAC Core Registers All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in the Command Register. PAGE 0 (PS1=0,PS0=0) OFFSET 00H Command Register ( CR ) 01H Page Start Register ( PSTART ) 02H Page Stop Register ...
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... AX88796 L PAGE 1 (PS1=0,PS0=1) OFFSET 00H Command Register ( CR ) 01H Physical Address Register 0 ( PARA0 ) 02H Physical Address Register 1 ( PARA1 ) 03H Physical Address Register 2 ( PARA2 ) 04H Physical Address Register 3 ( PARA3 ) 05H Physical Address Register 4 ( PARA4 ) 06H Physical Address Register 5 ( PARA5 ) 07H Current Page Register ...
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... Interrupt Status Register (ISR) Offset 07H (Read/Write) FIELD NAME 7 RST Reset Status : Set when AX88796 enters reset state and cleared when a start command is issued to the CR. NOTE: This bit does not generate an interrupt merely a status indicator. 6 RDC Remote DMA Complete Set when remote DMA operation has been completed This bit is cleared by writing a “ ...
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... These encoded configuration bits set the type of loop-back that performed. LB1 LB0 Mode 0 0 Mode 1 0 Mode CRC Inhibit CRC 0 : CRC appended by transmitter CRC inhibited by transmitter. 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 0 Normal operation 1 Internal AX88796 loop-back 0 PHYcevisor loop-back 35 ASIX ELECTRONICS CORPORATION ...
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... FIELD NAME 7 OWC Out of window collision 6:4 - Reserved 3 ABT Transmit Aborted Indicates the AX88796 aborted transmission because of excessive collision. 2 COL Transmit Collided Indicates that the transmission collided at least once with another station on the network Reserved 0 PTX Packet Transmitted Indicates transmission without error. ...
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... AX88796 L 5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap. Default value 15H. 5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap Segment 1. Default value 0cH. 5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) FIELD ...
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... AX88796 L 5.1.14 Test Register (TR) Offset 15H (Read) FIELD NAME 7:4 - Reserved 3 RST_TX 100BASE-TX in Reset : This signal indicates that 100BASE-TX logic of internal PHY reset. 2 RST_10B 10BASE-T in Reset : This signal indicates that 10BASE-T logic of internal PHY is in reset. 1 RST_B Reset Busy : This signal indicates that internal PHY is in reset. ...
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... AX88796 L 5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) FIELD NAME 7:0 DP Printer Data Port. Default is in input mode. Write /DOE of SPP_CPR register to logic “0” to enable print data output to printer as bi-directional mode. 5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read) FIELD ...
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... AX88796 L 5.2 The Embedded PHY Registers The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for the “ ...
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... AX88796 L 5.2.1 MR0 -- Control Register Bit Descriptions FIELD TYPE 0.15 (SW_RESET) R/W 0.14 (LOOPBACK) R/W 0.13(SPEED100) R/W 0.12 (NWAY_ENA) R/W 0.11 (PWRDN) R/W 0.10 (ISOLATE) R/W 0.9 (REDONWAY) R/W 0.8 (FULL_DUP) R/W 0.7 (COLTST) R/W 0.6:0 (RESERVED) NA 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Reset. Setting this bit will reset the PHY. All registers will be set to their default state. This bit is self-clearing. The default is 0. ...
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... AX88796 L 5.2.2 MR1 -- Status Register Bit Descriptions FIELD TYPE 1.15 (T4ABLE) R 1.14 (TXFULDUP) R 1.13 (TXHAFDUP) R 1.12 (ENFULDUP) R 1.11 (ENHAFDUP) R 1.10:7 (RESERVED) R 1.6 (NO_PA_OK) R 1.5 (NWAYDONE) R 1.4 (REM_FLT) R 1.3 (NWAYABLE) R 1.2 (LSTAT_OK) R 1.1 (JABBER) R 1.0 (EXT_ABLE) R 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION 100Base-T4 Ability. This bit will always Not able. 1: Able. 100Base-TX Full-Duplex Ability. This bit will always ...
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... AX88796 L 5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions FIELD TYPE 2.15:0 (OUI[3:18]) R 3.15:10 (OUI[19:24]) R 3.9:4 (MODEL[5:0]) R 3.3:0 (VERSION[3:0]) R 5.2.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions FIELD TYPE 4.15 (NEXT_PAGE) R/W 4.14 (ACK) R/W 4.13 (REM_FAULT) R/W 4.12:10 (PAUSE) R/W 4.9 (100BASET4) R/W 4.8 (100BASET_FD) R/W 4.7 (100BASETX) R/W 4.6 (10BASET_FD) R/W 4.5 (10BASET) R/W 4.4:0 (SELECT) R/W 5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit ...
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... AX88796 L 5.2.6 MR5 –Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit Descriptions FIELD TYPE 5.15 R (LP_NEXT_PAGE) 5.14 (LP_ACK) R 5.13 R (LP__MES_PAGE) 5.12 (LP_ACK2) R 5.11 (LP_TOGGLE) R 5.10:0 (MCF) R 5.2.7 MR6 – Autonegotiation Expansion Register Bit Descriptions FIELD TYPE 6.15:5 (RESERVED) R 6.4 R/LH (PAR_DET_FAULT) 6.3 R (LP_NEXT_PAGE_AB LE) 6.2 R (NEXT_PAGE_ABLE) 6.1 (PAGE_REC) R/LH 6.0 R (LP_NWAY_ABLE) 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Next Page ...
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... AX88796 L 5.2.8 MR7 –Next Page Transmit Register Bit Descriptions FIELD TYPE 7.15 (NEXT_PAGE) R/W 7.14 (ACK) R 7.13 (MESSAGE) R/W 7.12 (ACK2) R/W 7.11 (TOGGLE) R 7.10:0 (MCF) R/W 5.2.9 MR16 – PCS Control Register Bit Descriptions FIELD TYPE 16.15 (LOCKED) R 16.14-12 (UNUSED) R 16.11-4 (TESTBITS) R/W 16.3 (LOOPBACK) R/W 16.2 (SCAN) R/W 16.1 (FORCE R/W LOOPBACK) 16.0 (SPEEDUP R/W COUNTERS) 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Next Page. This bit indicates whether or not this is the last next page to be transmitted ...
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... AX88796 L 5.2.10 MR17 –Autonegotiation Register A Bit Descriptions FIELD TYPE 17.15-13 R 17.12 R 17.11 R 17.10 R 17.9 R 17.8 R 17.7 R 17.6 R 17.5 R 17.4 R 17.3 R 17.2 R 17.1 R 17.0 R 5.2.11 MR18 –Autonegotiation Register B Bit Descriptions FIELD TYPE 18.15 R 18.14 R 18.13 R 18.12 R 18.11 R 18.10 R 18.9 R 18.8 R 18.7 R 18.6 R 18.5 R 18.4 R 18.3 R 18.2 R 18.1 R 18.0 R 5.2.12 MR20 –User Defined Register Bit Descriptions FIELD TYPE 20.[15:0] R/W 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Reserved ...
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... AX88796 L 5.2.13 MR21 –RXER Counter Register Bit Descriptions FIELD TYPE 21.0 W 21.15:0 R 21.7:0 R 21.11:8 R 21.15:12 R 5.2.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions FIELD TYPE 28.15:9 (UNUSED) R 28.8 (BAD_FRM) R/LH 28.7 (CODE) R/LH 28.6 (APS) R 28.5 (DISCON) R/LH 28.4 (UNLOCKED) R/LH 28.3 (RXERR_ST) R/LH 28.2 (FRC_JAM) R/LH 28.1 (LNK100UP) R 28.0 (LNK10UP) R 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts this register in 8-bit counter mode ...
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... AX88796 L 5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions FIELD TYPE 29.15 (LOCALRST) R/W 29.14 (RST1) R/W 29.13 (RST2) R/W 29.12 (100_OFF) R/W 29.11 (LED_BLINK) R/W 29.10 (CRS_SEL) R/W 29.9 (LINK_ERR) R/W 29.8 (PKT_ERR) R/W 29.7 (PULSE_STR) R/W 29.6 (EDB) R/W 29.5 (SAB) R/W 29.4 (SDB) R/W 29.3 (CARIN_EN) R/W 29.2 (JAM_COL) R/W 29.1 (FEF-EN) R/W 29.0 (FX) R/W 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Management Reset. This is the local management reset bit. Writing logic 1 to this bit will cause the lower 16 registers and registers 28 and reset to their default values ...
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... AX88796 L 5.2.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions FIELD TYPE 30.15 (Test10TX) R/W 30.14 (RxPLLEn) R/W 30.13 (JAB_DIS) R/W 30.12:7 (UNUSED) R/W 30.6 (LITF_ENH) R/W 30.5 (HBT_EN) R/W 30.4 (ELL_EN) R/W 30.3 (APF_EN) R/W 30.2 (RESERVED) R/W 30.1 (SERIAL _SEL) R/W 30.0 (ENA_NO_LP) R/W 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION When high and 10Base-T is powered up, a continuous 10 MHz signal (1111) will be transmitted. This is only meant for testing. Default 0. ...
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... AX88796 L 5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions FIELD TYPE 31.15 (ERROR) R 31.14 R (RXERR_ST)/(LINK_ST AT_CHANGE) 31.13 (REM_FLT) R 31.12 R (UNLOCKED)/(JABBE R) 31.11 (LSTAT_OK) R 31.10 (PAUSE) R 31.9 (SPEED100) R 31.8 (FULL_DUP) R 31.7 (INT_CONF) R/W 31.6 (INT_MASK) R/W 31.5:3 R (LOW_AUTO__STATE) 31.2:0 R (HI_AUTO_STATE) 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION Receiver Error. When this bit indicates that a receive error has been detected ...
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... AX88796 L 6.0 CPU I/O Read and Write Functions 6.1 ISA bus type access functions. ISA bus I/O Read function Function Mode /CS /BHE Standby Mode H X Byte Access Word Access L L ISA bus I/O Write function Function Mode /CS /BHE Standby Mode H X Byte Access ...
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... AX88796 L 6.3 MC68K CPU bus type access functions. 68K bus I/O Read function Function Mode /CS /UDS Standby Mode H X Byte Access Word Access L L 68K bus I/O Write function Function Mode /CS /UDS Standby Mode H X Byte Access Word Access L L 6.4 MCS-51 CPU bus type access functions. ...
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... AX88796 L 6.5 CPU Access MII Station Management functions. Basic Operation The primary function of station management is to transfer control and status information about the PHY to a management entity. This function is accomplished by the MDC clock input from MAC entity, which has a maximum frequency of 12.5 MHz (for internal PHY only external PHY please refer to the relevant specification), along with the MDIO signal ...
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... AX88796 L 7.0 Electrical Specification and Timings 7.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability. ...
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... AX88796 L 7.4 A.C. Timing Characteristics 7.4.1 XTAL / CLOCK LCLK/XTALIN Tr CLKO Tod Symbol Description Tcyc CYCLE TIME Thigh CLK HIGH TIME Tlow CLK LOW TIME Tr/Tf CLK SLEW RATE Tod LCLK/XTALIN TO CLKO OUT DELAY 7.4.2 Reset Timing LCLK/XTALIN RESET /RESET Symbol Description Trst Reset pulse width 3-in-1 Local Bus Fast Ethernet Controller ...
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... AX88796 L 7.4.3 ISA Bus Access Timing (1) Read cycle: Tsu(AEN) AEN /BHE SA[9:0],/CS Tv(CS16-A) /IOCS16 Tv(RDY) RDY *1 Z-pull up /IORD Read Data SD[15:0](Dout) Symbol Description Tsu(AEN) AEN SETUP TIME Th(AEN) AEN HOLD TIME Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(CS16-A) /IOCS16 VALID FROM SA[9:0], /CS, /BHE AND ...
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... AX88796 L (2) Write cycle: Tsu(AEN) AEN /BHE SA[9:0],/CS /IOCS16 /IOW Write Data SD [15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(AEN) AEN SETUP TIME Th(AEN) AEN HOLD TIME Tv(CS16-A) /IOCS16 VALID FROM SA[9:0], /CS, /BHE AND AEN Tdis(CS16-A) /IOCS16 DISABLE FROM SA[9:0], /CS, /BHE AND ...
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... AX88796 L 7.4.4 80186 Type I/O Access Timing (1) Read cycle: /BHE SA[9:0],/CS Tv(RDY) RDY *1 Z-pull up /IORD Read Data SD[15:0](Dout) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(RDY) RDY VALID FROM SA,/CS AND /BHE Tdis(RDY) RDY DISABLE FROM SA[9:0]=310 VALID, /CS AND /BHE Ten(RD) OUTPUT ENABLE TIME FROM /IORD ...
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... AX88796 L (2) Write Cycle /BHE SA[9:0],/CS /IOWR Write Data SD[15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(WR) DATA SETUP TIME Th(WR) DATA HOLD TIME Tiorw /IOWR WIDTH TIME Tcycle CYCYLE TIME FOR EVERY DATA PORT WRITE 3-in-1 Local Bus Fast Ethernet Controller ...
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... AX88796 L 7.4.5 68K Type I/O Access Timing (1) Read cycle SA[9:1],/CS /UDS,/LDS high (Read) R/W Tv(DTACK) /DTACK Z-pull up (Read Data) SD[15:0](Dout) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(DTACK) DACK VALID FROM /UDS OR /LDS Tdis(DTACK) DACK DISABLE FROM /UDS OR /LDS Ten(DS) OUTPUT ENABLE TIME FROM /UDS OR /LDS ...
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... AX88796 L (2) Write cycle SA[9:1],/CS Tv(DS-WR) /UDS,/LDS (Write) R/W Tv(DTACK) /DTACK*1 (Write Data) SD[15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(DS-WR) /UDS OR /LDS VALID FROM /UDS OR /LDS Tdis(WR-DS) /W DISABLE FROM /UDS OR /LDS Tv(DTACK) DACK VALID FROM /UDS OR /LDS Tdis(DTACK) DACK DISABLE FROM /UDS OR /LDS ...
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... AX88796 L 7.4.6 8051 Bus Access Timing (1) Read cycle /PSEN Tsu(PSEN) SA[9:0],CS Tv(RDY) /RDY*1 Z-pull up /IORD Read Data SD[7:0](Dout) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(PSEN) /PSEN SETUP TIME Th(PSEN) /PSEN HOLD TIME Ten(RD) OUTPUT ENABLE TIME FROM /IORD Tdis(RD) OUTPUT DISABLE TIME FROM /IORD ...
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... AX88796 L (2) Write cycle /PSEN Tsu(PSEN) SA[9:0],CS /IOWR Write Data SD[7:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(PSEN) /PSEN SETUP TIME Th(PSEN) /PSEN HOLD TIME Tsu(WR) DATA SETUP TIME Th(WR) DATA HOLD TIME T IOWR WIDTH iowr Tcycle I/O CYCLE WIDTH TIME ...
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... AX88796 L 7.4.7 MII Timing TXCLK TXD<3:0> TXEN RXCLK RXD<3:0> RXDV RXER Symbol Description Ttclk Cycle time(100Mbps) Ttclk Cycle time(10Mbps) Ttch high time(100Mbps) Ttch high time(10Mbps) Trch low time(100Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold time Trclk Cycle time(100Mbps) ...
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... AX88796 L 8.0 Package Information pin 1 b θ SYMBOL θ 3-in-1 Local Bus Fast Ethernet Controller MILIMETER MIN. NOM 0.05 0.1 1.35 1.40 0.17 0.22 13.90 14.00 19.90 20.00 0.5 15.60 16.00 21.00 22.00 0.45 0.60 1.00 0° 65 ASIX ELECTRONICS CORPORATION MAX 0.15 1.45 1.6 0.27 14.10 20.10 16.40 23.00 0.75 7° ...
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... AX88796 L 9.0 Ordering Information AX88796 Product name 3-in-1 Local Bus Fast Ethernet Controller L Package LQFP 66 ASIX ELECTRONICS CORPORATION F F: Lead Free ...
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... AX88796 L Appendix A: Application Note 1 A.1 Using Crystal 25MHz AX88796 XTALIN 25MHz Crystal 33pf Note : The capacitors (33pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz AX88796 XTALIN 3.3V Power OSC 25MHz 3-in-1 Local Bus Fast Ethernet Controller ...
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... AX88796 L Appendix B: Power Consumption Reference Data The following reference data of power consumption are measured base on prime application, that is AX88796 + EEPROM, at 3.3V/25 °C room temperature. Item 1 Power save mode ( Power Down register bit set to “1” asserted) 2 Idel without Link 3 Idel with 10M Link ...
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... Solution: Please using word mode for high performance. MC68008 has only 8-bit bus, so AX88796 can’t support this CPU. 3. When AX88796 transmit a packet and the packet is collided for 16 times. The packet will be reported as as PTX bit asserted rather than TXE asserted. ...
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... AX88796 L 5. Listed limitations (as following table) must consider when connecting with CPU’s IO cycle is less then 160 ns. Description: There are 4 limitations in AX88796 must not excess when using AX88796 All limitations timing information has marked in corresponding timing diagram 6 . When /RDY not connect, following steps must include in driver when “READ” data port ...
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... IF Bit 2 (Link Status) is ZERO (link down), Read MII Register 1 again. IF Bit 2 (Link Status) is ONE (link up), Exit the watchdog timer routine IF Bit 2 (Link Status) is still ZERO (link down Write MII Register 0 with 0x3900 (Power down AX88796's PHY) * Set the PowerDownFlag to TRUE } Exit the watchdog timer routine ...
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... AX88796 L Demonstration Circuit (A) : AX88796 with ISA Bus + HomePNA 1M8 PHY AX88796 10BASE-T/100BASE-TX & 1M HomePNA Application with NS83851 PHYceiver. (reference only)(ISA Mode) GND RESET 5V C60 C59 + 0.1u 47u/16v DIP 100mil & SMD1206 GND IOWR# IORD# JP2 is setting IRQ JP2 IRQ IRQ3 ...
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... AX88796 L SA[0..9] SD[0..15] SA0 BHE# SA1 BHE# IORD# SA2 IORD# IOWR# SA3 IOWR# AEN SA4 AEN RESET SA5 RESET IREQ SA6 10 IRQ RDY SA7 11 RDY IOIS16# SA8 12 IOIS16# SA9 15 3.3V SD0 42 3.3V GND SD1 41 GND SD2 39 SD3 38 SD4 37 SD5 36 SD6 35 SD7 33 SD8 32 SD9 31 SD10 30 SD11 ...
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... AX88796 L RESET RESET RXER RXER RXDV RXDV COL COL CRS CRS RXCK RXCK RXD0 RXD0 RXD1 RXD1 RXD2 RXD2 RXD3 TXD3 RXD3 TXCK TXD2 TXCK TXD1 TXEN TXD0 TXEN TXD0 TXEN TXD0 TXD1 TXCK TXCLK TXD1 TXD2 TXD2 TXD3 R28 20 RXD3 ...
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... AX88796 L R34 0 ZVREG C47 C61 + 4.7uF/16V 0.01u R36 SMD 1206 49.9 TPOP TPOP TPON TPON TPIP TPIP TPIN TPIN R43 R42 49.9 49.9 C57 C56 0.1u 0.001u 3.3V 3.3V C45 R32 R31 0.1u 49.9 49.9 TIP TIP RING RING GND GND R35 49 TD+ TX TD- TX RD+ ...
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... AX88796 L Revision Date(M/D/Y) 01/24//02 V 1.7 06/18/02 V1.8 08/19/03 V1.9 09/19/03 V2.0 10/30/03 V2.1 02/18/05 V2.2 09/12/05 V2.3 TEL: 886-3-5799500 FAX: 886-3-5799558 Email: Web: 3-in-1 Local Bus Fast Ethernet Controller Comment 1 Remove Tally counter at MAC register list 2 Modify RDY timing diagram in ISA and 186 mode 3 Remove BOS bit in DCR register 4 Include LED current sink value Schematic change for hi-voltage Cap, change from 0 ...