EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
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Features
Figure 7. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
VCC
1
24
CLK1
INPUT
INPUT
2
23
I/O
3
22
I/O
I/O
I/O
4
21
I/O
I/O
5
20
I/O
6
19
I/O
I/O
I/O
7
18
I/O
8
17
I/O
I/O
I/O
9
16
I/O
10
15
I/O
INPUT
11
14
INPUT
CLK2
GND
12
13
24-Pin SOIC
EP610
Altera Corporation
High-performance, 16-macrocell Classic EPLD
Combinatorial speeds with t
Counter frequencies of up to 100 MHz
Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming
file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
24-pin small-outline integrated circuit (plastic SOIC only)
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
28-pin plastic J-lead chip carrier (PLCC)
CLK1
1
24
VCC
INPUT
2
23
INPUT
I/O
3
22
I/O
I/O
4
21
I/O
I/O
5
20
I/O
I/O
6
19
I/O
I/O
7
18
I/O
I/O
8
17
I/O
I/O
9
16
I/O
I/O
10
15
I/O
INPUT
11
14
INPUT
GND
12
13
CLK2
24-Pin DIP
EP610
EP610I
EP610 EPLD
as fast as 10 ns
PD
Figure
7):
4
3
2
1
28
27
26
I/O
5
I/O
6
I/O
7
I/O
8
EP610
I/O
9
I/O
10
NC
11
12
13
14
15
16
17
18
28-Pin PLCC
EP610
EP610I
25
I/O
24
I/O
23
I/O
22
I/O
21
I/O
20
I/O
19
NC
755