m37516e6hp Renesas Electronics Corporation., m37516e6hp Datasheet
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m37516e6hp Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7516 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7516 group is designed for the household products and office automation equipment and includes serial I/O functions, ...
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Group FUNCTIONAL BLOCK Fig.2 Functional block diagram Rev.1.01 Jul 01, 2003 page ...
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Group Table 1 Pin description Pin Name Power source CC SS CNV input CNV SS SS Reference V REF voltage input Analog power AVss source input Reset input RESET Clock input X IN Clock output X ...
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Group PART NUMBERING Product name M37516 M 8 – XXX HP Fig. 3 Part numbering Rev.1.01 Jul 01, 2003 page Package type HP : 48P6Q-A ROM number Omitted in One Time PROM version shipped in blank ...
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Group GROUP EXPANSION Mitsubishi plans to expand the 7516 group as follows. Memory Type Support for mask ROM, One Time PROM, and flash memory ver- sions. Memory Size Flash memory size ......................................................... 32 K bytes Mask ROM size ................................................. ...
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... Currently planning products are listed below. Table 2 Support products ROM size (bytes) Product name ROM size for User in ( 16384 M37516M4-XXXHP (16254) M37516M6-XXXHP 24576 M37516E6-XXXHP (24446) M37516E6HP M37516M8-XXXHP 32768 (32638) M37516F8HP Rev.1.01 Jul 01, 2003 page RAM size (bytes) Package ) 512 640 ...
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Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 7516 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on ...
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Group ...
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Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can ...
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Group [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure of CPU mode register Rev.1.01 Jul 01, 2003 ...
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Group MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine ...
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Group ...
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Group I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input ...
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Group ( ...
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Group ( ...
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Group (17) Port P4 3 Serial I/O2 input/output comparison signal control bit Port latch S ...
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Group INTERRUPTS Interrupts occur by 17 sources among 17 sources: seven external, nine internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for ...
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Group Table 6 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD INT 2 0 FFFB 3 SCL, SDA FFF9 INT 1 FFF7 4 INT 5 FFF5 2 INT 3 ...
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Group ...
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Group TIMERS The 7516 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding ...
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Group ...
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Group SERIAL I/O SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation CLK ...
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Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can ...
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Group Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection occurs at the same time that ...
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Group (SIOSTS : address 0019 ...
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Group SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit ...
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Group ...
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Group S CMP2 Fig output operation CMP2 Rev.1.01 Jul 01, 2003 page Judgement of I/O data comparison ...
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Group 2 MULTI-MASTER I C-BUS INTERFACE 2 The multi-master I C-BUS interface is a serial communications cir- 2 cuit, conforming to the Philips I C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchro- n ...
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Group Data Shift Register (S0)] 002B 2 The I C data shift register (S0 : address 002B register to store receive data and write transmit data. When transmit data is written into this register ...
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Group Clock Control Register (S2)] 002F 2 The I C clock control register (address 002F control, SCL mode and SCL frequency. •Bits SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. ...
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Group Control Register (S1D)] 002E 2 The I C control register (address 002E cation format. •Bits Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be ...
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Group Status Register (S1)] 002D 2 The I C status register (address 002D terface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “0000 ...
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Group •Bit 6: Communication mode specification bit (transfer direc- tion specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting ...
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Group START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I register (address 002D ) at the same time after writing the slave 16 2 address to the I C data shift ...
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Group START/STOP Condition Control Register (S2D)] 0030 16 2 The I C START/STOP condition control register (address 0030 controls START/STOP condition detection. •Bits START/STOP condition set bit (SSC4–SSC0) SCL release time, setup time, ...
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Group ...
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Group Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 ...
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Group Precautions when using multi-master I BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master 2 I C-BUS interface are described below. 2 • ...
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Group PULSE WIDTH MODULATION (PWM) The 7516 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input X vided by 2. Data Setting The PWM output pin also functions as port ...
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Group ...
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Group A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion [AD Control ...
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Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit ...
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Group RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned “H” level (the power source voltage ...
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Group ( ...
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Group CLOCK GENERATING CIRCUIT The 7516 group has two built-in oscillation circuits: main clock X X oscillation circuit and sub clock X OUT circuit. An oscillation circuit can be formed by connecting a reso- nator between X and X ...
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Group Notes on middle-speed mode automatic switch set bit When the middle-speed mode automatic switch set bit is set to “1” while operating in the low-speed mode, by detecting the rising/fall- ing edge of the SCL or SDA pin, ...
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Group ...
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Group FLASH MEMORY MODE The M37516F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when V CC when and V ...
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Group (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Process- ing Unit (CPU). In CPU rewrite mode, only the User ROM area ...
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Group Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads ...
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Group Notes 1: When starting the MCU in the single-chip mode, supply 4 5 the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set bits 6, 7 (main clock division ratio selection ...
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Group Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock frequency 4.0 MHz or less ...
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Group Software Commands (CPU Rewrite Mode) Table 14 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. ...
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Group Erase All Blocks Command (20 / writing the command code “20 ” in the first bus cycle and the 16 confirmation command code “20 ” in the second bus cycle that 16 follows, the operation of ...
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Group Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading an ...
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Group Full Status Check By performing full status check possible to know the execu- tion results of erase and program operations. Figure 62 shows a Read status register ...
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Group Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ...
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Group ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared with ...
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Group (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc built-in flash memory. Use the ex- clusive ...
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Group (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This ...
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Group Table 16 Description of pin function (Standard Serial I/O Mode ...
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Group / ...
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Group Software Commands (Standard Serial I/O Mode) Table 17 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 17 Software commands (Standard serial I/O mode) Control command 1 Page read ...
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Group Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following ...
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Group Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “50 code is sent with the 1st byte, the aforementioned bits are cleared. When ...
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Group Erase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 ” command code with the 1st byte. 16 (2) Transfer the verify ...
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Group Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA ” command code with the 1st byte. 16 (2) Transfer the program size with ...
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Group Version Information Output Command This command outputs the version information of the control pro- gram stored in the Boot ROM area. Execute the version information output command as explained here following ...
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Group ID Check This command checks the ID code. Execute the boot ID check command as explained here following ...
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Group Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status ...
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Group Status Register 1 (SRD1) The status register 1 indicates the status of serial communica- tions, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writ- ing the ...
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Group Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 75 shows a flowchart of the full status check and explains how to remedy errors which occur. Read ...
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Group Example Circuit Application for Standard Serial I/O Mode Figure 76 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information ...
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Group Flash memory Electrical characteristics Table 20 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage Input ...
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Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” Af- ter a reset, initialize flags which affect program ...
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Group DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical ...
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Group ELECTRICAL CHARACTERISTICS Table 23 Absolute maximum ratings (Executing flash memory mode, flash memory electrical characteristics is applied.) Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input ...
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Group Table 25 Recommended operating conditions ( 2 – °C, unless otherwise noted Symbol “H” peak output current I OH(peak) I OL(peak) “L” peak output current I OL(peak) ...
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Group Table 26 Electrical characteristics (V = 2 – °C, unless otherwise noted Symbol Parameter “H” output voltage P0 – – ...
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Group Table 27 Electrical characteristics (V = 2 – °C, unless otherwise noted Symbol Parameter Test conditions High-speed mode f MHz IN ...
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Group Table 28 A-D converter characteristics (V = 2 Symbol Parameter – Resolution – Absolute accuracy (excluding quantization error) t Conversion time CONV R Ladder resistor ...
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Group TIMING REQUIREMENTS Table 29 Timing requirements ( 4 – °C, unless otherwise noted Symbol t (RESET) Reset input “L” pulse width W ...
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Group Table 31 Switching characteristics 4 – °C, unless otherwise noted Symbol Serial I/O1 clock output “H” pulse width ...
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Group 2 MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS 2 Table 33 Multi-master I C-BUS bus line characteristics Symbol t Bus free time BUF t Hold time for START condition HD;STA t Hold time for SCL clock = “0” LOW ...
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Group Measurement output pin CMOS output Fig. 79 Circuit for measuring output switching characteris- tics (1) Rev.1.01 Jul 01, 2003 page Measurement output pin 100pF Fig. 80 Circuit for measuring output switching characteris- tics (2) 1 ...
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Group CNTR 0 CNTR 1 INT to INT 0 3 RESET CLK1 S CLK2 IN2 OUT2 Fig. 81 Timing diagram Rev.1.01 Jul 01, 2003 page ...
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Group PACKAGE OUTLINE MMP 48P6Q-A EIAJ Package Code JEDEC Code LQFP48-P-77-0.50 – Rev.1.01 Jul 01, 2003 page Weight(g) Lead ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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REVISION HISTORY Rev. Date Page 0.1 – First edition issued Feb. 03, 2000 1.0 1 “ Memory size” of “FEATURES” is revised. Sep. 05, 2002 1 “ Power dissipation” of “FEATURES” is revised. 2 Figure 2 is partly revised. 3 ...