EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

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Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Symbol
Parameter
t
Input pad and buffer delay
IN
t
I/O input pad and buffer delay
IO
t
Logic array delay
LAD
t
Output buffer and pad delay
OD
t
Output buffer enable delay
ZX
t
Output buffer disable delay
XZ
t
Register setup time
SU
t
Register hold time
H
t
Array clock delay
IC
t
Global clock delay
ICS
t
Feedback delay
FD
t
Register clear time
CLR
Notes to tables:
(1)
These values are specified in
(2)
See
Application Note 78 (Understanding MAX 5000 & Classic Timing)
timing parameters.
(3)
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4)
Sample-tested only for an output change of 500 mV.
(5)
The f
values represent the highest frequency for pipelined data.
MAX
(6)
Measured with a device programmed as a 16-bit counter.
(7)
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
Condition
EP610-25
Min
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
11.0
10.0
Table 3 on page
758.
Classic EPLD Family Data Sheet
EP610-30
EP610-35
Max
Min
Max
Min
8.0
9.0
2.0
2.0
11.0
14.0
6.0
7.0
6.0
7.0
6.0
7.0
11.0
12.0
10.0
10.0
13.0
16.0
1.0
1.0
3.0
5.0
13.0
16.0
in this data book for information on internal
Unit
Max
11.0
ns
2.0
ns
15.0
ns
9.0
ns
9.0
ns
9.0
ns
ns
ns
17.0
ns
0.0
ns
8.0
ns
17.0
ns
763