EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

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Classic EPLD Family Data Sheet
General
Description
Figure 12. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
2
(3)
INPUT
3
(4)
INPUT
4
(5)
INPUT
1
(2)
CLK1
5
(6)
6
(7)
7
(8)
8
(9)
(10)
9
(11)
10
11
(12)
12
(13)
13
(14)
14
(15)
15
(16)
16
(18)
17
(19)
INPUT
18
(20)
INPUT
19
(21)
INPUT
768
Altera EP910 devices can implement up to 450 usable gates of SSI and MSI
logic functions. EP910 devices have 24 macrocells, 12 dedicated input
pins, 24 I/O pins, and 2 global clock pins (see
can access signals from the global bus, which consists of the true and
complement forms of the dedicated inputs and the true and complement
forms of either the output of the macrocell or the I/O input. The CLK1 and
CLK2 signals are the dedicated clock inputs for the registers in macrocells
13 through 24 and 1 through 12, respectively.
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Global
Bus
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
Figure
12). Each macrocell
INPUT
INPUT
INPUT
CLK2
(40)
Macrocell 1
(38)
Macrocell 2
(37)
Macrocell 3
(36)
Macrocell 4
(35)
Macrocell 5
(34)
Macrocell 6
Macrocell 7
(33)
Macrocell 8
(32)
Macrocell 9
(31)
Macrocell 10
(30)
Macrocell 11
(29)
Macrocell 12
(28)
INPUT
INPUT
INPUT
Altera Corporation
39
(43)
(42)
38
37
(41)
(24)
21
36
35
34
33
32
31
30
29
28
27
26
25
(27)
24
(26)
23
(25)
22