25AA040TISN Microchip Technology Inc., 25AA040TISN Datasheet
25AA040TISN
Manufacturer Part Number
25AA040TISN
Description
SOIC-8
Manufacturer
Microchip Technology Inc.
Datasheet
1.25C040P.pdf
(22 pages)
Specifications of 25AA040TISN
Date_code
08+
Device Selection Table
Features
• Low-power CMOS technology
• 512 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
• Built-in write protection
• Sequential read
• High reliability
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
Description
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040
Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface™ (SPI™) compatible serial
bus. The bus signals required are a clock input (SCK)
plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a Chip
Select (CS) input.
*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices. SPI is a
trademark of Motorola Corporation.
2003 Microchip Technology Inc.
25AA040
25LC040
- Write current: 3 mA typical
- Read current: 500 A typical
- Standby current: 500 nA typical
- Protect none, 1/4, 1/2 or all of array
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
- Endurance: 1M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
- Industrial (I):
- Automotive (E) (25C040):
Number
25C040
Part
1.8-5.5V
2.5-5.5V
4.5-5.5V
Range
V
*
CC
) is a 4 Kbit serial Electrically
Max. Clock
Frequency
4K SPI
1 MHz
2 MHz
3 MHz
-40 C to +85 C
-40°C to +125°C
25AA040/25LC040/25C040
™
Ranges
Temp.
I,E
Bus Serial EEPROM
I
I
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).
Package Types
Block Diagram
HOLD
SCK
TSSOP
WP
SO
SOIC
CS
PDIP
SI
I/O Control
Register
Status
Logic
HOLD
V
V
WP
WP
SO
SO
CS
CS
V
SS
SS
SO
CS
CC
1
2
3
4
1
2
3
4
1
2
3
4
V
V
CC
SS
Memory
Control
Logic
8
7
6
5
8
7
6
5
8
7
6
5
XDEC
SCK
SI
V
WP
V
HOLD
SCK
SI
V
HOLD
SCK
SI
SS
CC
CC
DS21204D-page 1
Sense Amp.
R/W Control
Y Decoder
HV Generator
EEPROM
Latches
Page
Array
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