AT91FR40162SCJ ATMEL Corporation, AT91FR40162SCJ Datasheet
AT91FR40162SCJ
Manufacturer Part Number
AT91FR40162SCJ
Description
BGA
Manufacturer
ATMEL Corporation
Datasheet
1.AT91FR40162SCJ.pdf
(210 pages)
Specifications of AT91FR40162SCJ
Date_code
08+
- Current page: 1 of 210
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1. Description
The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained appli-
cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-
programmed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
Incorporates the ARM7TDMI
256K Bytes of On-chip SRAM
1024K Words 16-bit Flash Memory (2M bytes)
Fully Programmable External Bus Interface (EBI)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
2 USARTs
Programmable Watchdog Timer
Advanced Power-saving Features
Fully Static Operation:
2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
-40 C to 85 C Temperature Range
Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
– 32-bit Data Bus, Single-clock Cycle Access
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
– CPU and Peripherals Can be De-activated Individually
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85 C
™
(In-circuit Emulation)
®
ARM
®
Thumb
®
Processor Core
AT91
ARM
Microcontrollers
AT91FR40162S
Preliminary
®
Thumb
6174B–ATARM–07-Nov-05
®
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