ATF1504AS15JI44 ATMEL Corporation, ATF1504AS15JI44 Datasheet

ATF1504AS15JI44

Manufacturer Part Number

ATF1504AS15JI44

Description

PLCC44

Manufacturer

ATMEL Corporation

Datasheet

1.ATF1504AS10JC68.pdf (35 pages)

Specifications of ATF1504AS15JI44

Date_code

06+

Current page: 1 of 35
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Features

•

Enhanced Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

Advanced Power Management Features

Available in Commercial and Industrial Temperature Ranges

Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP

Advanced EE Technology

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

3.3V or 5.0V I/O Pins

Security Fuse Feature

Green (Pb/Halide-fee/RoHS Compliant) Package Options

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

Transparent – Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

– Automatic µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Circuits on Inputs and I/Os

– Reduced-power Feature per Macrocell

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Power-up Reset Option

High-

performance

Complex

Programmable

Logic Device

ATF1504AS

ATF1504ASL

Rev. 0950O–PLD–7/05

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