ATMEGA8515L8AU ATMEL Corporation, ATMEGA8515L8AU Datasheet - Page 26

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ATMEGA8515L8AU

Manufacturer Part Number
ATMEGA8515L8AU
Description
TQFP44
Manufacturer
ATMEL Corporation
Datasheet

Specifications of ATMEGA8515L8AU

Date_code
10+
Address Latch Requirements
ATmega8515(L)
26
The control bits for the External Memory Interface are located in three registers, the
MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and
the Special Function IO Register – SFIOR.
When the XMEM interface is enabled, it will override the settings in the data direction
registers corresponding to the ports dedicated to the interface. For details about this port
override, see the alternate functions in section “I/O Ports” on page 59. The XMEM inter-
face will auto-detect whether an access is internal or external. If the access is external,
the XMEM interface will output address, data, and the control signals on the ports
according to Figure 13 (this figure shows the wave forms without wait states). When
ALE goes from high to low, there is a valid address on AD7:0. ALE is low during a data
transfer. When the XMEM interface is enabled, also an internal access will cause activ-
ity on address-, data-, and ALE ports, but the RD and WR strobes will not toggle during
internal access. When the External Memory Interface is disabled, the normal pin and
data direction settings are used. Note that when the XMEM interface is disabled, the
address space above the internal SRAM boundary is not mapped into the internal
SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal
latch (typically “74x573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The external memory interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
D to Q propagation delay (t
)
pd
Data setup time before G low (t
Data (address) hold time after G low (
The external memory interface is designed to guaranty minimum address hold time after
G is asserted low of t
= 5 ns (refer to t
h
204). The D to Q propagation delay (t
ing the access time requirement of the external component. The data setup time before
G low (t
) must not exceed address valid to ALE low (t
su
(dependent on the capacitive load).
Figure 12. External SRAM Connected to the AVR
AD7:0
ALE
AVR
A15:8
RD
WR
)
su
)
th
/t
in Table 98 to Table 105 on page
LAXX_LD
LLAXX_ST
) must be taken into consideration when calculat-
pd
) minus PCB wiring delay
AVLLC
D[7:0]
D
Q
A[7:0]
G
SRAM
A[15:8]
RD
WR
2512J–AVR–10/06

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