EPF10K30RC2083

Manufacturer Part NumberEPF10K30RC2083
DescriptionQFP
ManufacturerAltera Corporation
EPF10K30RC2083 datasheet
 

Specifications of EPF10K30RC2083

Date_code04+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 59/128

Download datasheet (2Mb)Embed
PrevNext
Table 32. LE Timing Microparameters (Part 1 of 2)
Symbol
t
LUT delay for data-in
LUT
t
LUT delay for carry-in
CLUT
t
LUT delay for LE register feedback
RLUT
t
Data-in to packed register delay
PACKED
t
LE register enable delay
EN
t
Carry-in to carry-out delay
CICO
t
Data-in to carry-out delay
CGEN
t
LE register feedback to carry-out delay
CGENR
t
Cascade-in to cascade-out delay
CASC
t
LE register control signal delay
C
t
LE register clock-to-output delay
CO
t
Combinatorial delay
COMB
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
Tables 32
through
36
describe the FLEX 10K device internal timing
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis.
Tables 37
timing parameters.
Note (1)
Parameter
OE Register
PRN
D
Q
t
XZBIDIR
t
ZXBIDIR
CLRN
t
OUTCOBIDIR
Output Register
PRN
D
Q
t
CLRN
t
Input Register
PRN
D
Q
CLRN
through
38
describe FLEX 10K external
Bidirectional
Pin
INSUBIDIR
INHBIDIR
Conditions
59