W981616BH7 Winbond, W981616BH7 Datasheet

W981616BH7

Manufacturer Part Number

W981616BH7

Description

TSOP/28

Manufacturer

Winbond

Datasheet

1.W981616BH7.pdf (41 pages)

Specifications of W981616BH7

Date_code

04+

Current page: 1 of 41
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GENERAL DESCRIPTION

W981616BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

512K words

W981616BH delivers a data bandwidth of up to 400M bytes per second (-5). For different applications

the W981616BH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to

200Mhz/CL3. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3. For

handheld device application, we also provide a low power option, the grade of –7L, with Self Refresh

Current under 200µA

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W981616BH is ideal for main memory in

high performance applications.

FEATURES

PART NUMBER INFORMATION

Part Number

W981616BH-5

W981616BH-6

W981616BH-7

W981616BH-7L

3.3V ±0.3V power supply

Up to 200 MHz clock frequency

524,288 words x 2 banks x 16 bits organization

Self Refresh current: standard and low power

CAS latency: 2 and 3

Burst Length: 1, 2, 4, 8, and full page

2 banks

16 bits. Using pipelined architecture and 0.175 m process technology,

512K

Speed (CL=3)

200MHz

166MHz

143MHz

- 1 -

2 BANKS

Burst read, Single Write Mode

Byte data controlled by UDQM and LDQM

Auto-precharge and controlled precharge

4K refresh cycles/64 mS

Interface: LVTTL

Packaged in 50-pin, 400 mil TSOP II

Publication Release Date: May 2001

Self Refresh current(MAX.)

16 BITS SDRAM

W981616BH

200

1mA

Revision A3

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