CY7C344-25HMB Cypress Semiconductor Corporation., CY7C344-25HMB Datasheet
CY7C344-25HMB
Manufacturer Part Number
CY7C344-25HMB
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheets
1.CY7C344-25HMB.pdf
(15 pages)
2.CY7C344-25HMB.pdf
(16 pages)
3.CY7C344-25HMB.pdf
(16 pages)
Specifications of CY7C344-25HMB
Package
JLCC
Date_code
05+/06+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Cypress Semiconductor Corporation
Document #: 38-03006 Rev. **
Features
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344 represents the dens-
est EPLD of this size. Eight dedicated inputs and 16 bidirec-
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current
(mA)
Maximum Standby Current
(mA)
Note:
• High-performance, high-density replacement for TTL,
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
1.
Logic Block Diagram
74HC, and custom logic
package
15(22)
15(23)
27(6)
28(7)
Numbers in () refer to J-leaded packages.
INPUT
INPUT
INPUT
INPUT
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
64 EXPANDER PRODUCT TERM ARRAY
[ 1 ]
G
O
B
A
B
U
S
L
L
Commercial
Military
Industrial
Commercial
Military
Industrial
•
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
3901 North First Street
INPUT
INPUT/CLK 2(9)
INPUT
INPUT
32
13(20)
14(21)
1(8)
O
C
O
N
T
R
O
L
I
7C344-15
tional I/O pins communicate to one logic array block. In the
CY7C344 LAB there are 32 macrocells and 64 expander prod-
uct terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344 makes it a natural for
all types of applications. With just this one device, the designer
can implement complex state machines, registered logic, and
combinatorial “glue” logic, without using multiple chips. This
architectural flexibility allows the CY7C344 to replace multi-
chip TTL solutions, whether they are synchronous, asynchro-
nous, combinatorial, or all three.
200
220
150
170
15
C344–1
•
32-Macrocell MAX® EPLD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
San Jose
10(17)
11(18)
12(19)
17(24)
18(25)
19(26)
20(27)
23(2)
24(3)
25(4)
26(5)
3(10)
4(11)
5(12)
6(13)
9(16)
INPUT/CLK
Pin Configurations
7C344-20
INPUT
INPUT
INPUT
•
200
220
220
150
170
170
20
I/O
I/O
I/O
INPUT/CLK
CA 95134
INPUT
INPUT
INPUT
5
6
7
8
9
10
11
GND
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CC
12 13 14 1516 1718
4 3 2
Top View
CerDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
HLCC
Revised July 18, 2000
1
28 27 26
•
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY7C344
7C344-25
408-943-2600
25
24
23
22
21
20
19
INPUT
INPUT
I/O
I/O
I/O
I/O
V
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
200
220
220
150
170
170
CC
25
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
C344–2
C344–3
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