FW323-06 Agere Systems, FW323-06 Datasheet

FW323-06

Manufacturer Part Number

FW323-06

Description

Manufacturer

Agere Systems

Datasheet

1.FW323-06.pdf (92 pages)

Specifications of FW323-06

Case

QFP-142

Date_code

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

FW323-06

Manufacturer:

AGERE

Quantity:

Current page: 1 of 92
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FW323 06

1394A PCI PHY/Link Open Host Controller Interface

Features

1394a-2000 OHCI link and PHY core function in a

single device:

— Single-chip link and PHY enable smaller, simpler,

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current Microsoft

— Demonstrated interoperability with existing, as well

— Feature-rich implementation for high performance

— Supports low-power system designs (CMOS

— Provides LPS, LKON, and CNA outputs to support

OHCI:

— Complies with the 1394 OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable via

— Complies with Microsoft Windows logo program

— Listed on Windows hardware compatibility list

— Compatible with Microsoft Windows and MacOS

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming physical

— Supports notification (via interrupt) of a failed

1394a-2000 PHY core:

— Compliant with IEEE

— Provides three fully compliant cable ports, each

more efficient motherboard and add-in card

designs

Windows

as older, 1394 ™ consumer electronics and periph-

erals products

in common applications

implementation, power management features)

legacy power management implementations

EEPROM to operate in either OHCI 1.0 or

OHCI 1.1 mode

system and device requirements

http://www.microsoft.com/hcl/results.asp

operating systems

descriptor-based DMA engines

read and write requests

High Performance Serial Bus (Supplement)

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

drivers and common applications

1394a-2000, Standard for a

— Supports extended BIAS_HANDSHAKE time for

— While unpowered and connected to the bus, will

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

— 25 MHz crystal oscillator and internal PLL provide

— Interoperable across 1394 cable with 1394 phys-

— Provides node power-class information signaling

— Supports ack-accelerated arbitration and fly-by

— Supports arbitrated short bus reset to improve

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

— Reports cable power fail interrupt when voltage at

— Provides separate cable bias and driver termina-

Link:

— Cycle master and isochronous resource manager

— Supports 1394a-2000 acceleration features

PCI:

— Revision 2.2 compliant

— 33 MHz/32-bit operation

— Programmable burst size thresholds for PCI data

— Supports optimized memory read line, memory

— Supports PCI Bus Power Management Interface

— Supports CLKRUN# protocol per PCI Mobile

— Supports Mini PCI Specification v1.0, including

— Global byte swap function

— CardBus support per PC Card Standard

enhanced interoperability with camcorders

not drive TPBIAS on a connected port even if

receiving incoming bias voltage on that port

PHY core-link interface

a 50 MHz internal link-layer controller clock as

well as transmit/receive data at 100 Mbits/s,

200 Mbits/s, and 400 Mbits/s

ical layers (PHY core) using 5 V supplies

for system power management

concatenation

utilization of the bus

packets

CPS pin falls below 7.5 V

tion voltage supply for each port

capable

transfer

read multiple, and memory write invalidate burst

commands

Specification v.1.1, including D3cold wakeups

Design Guide

Mini PCI power requirements

Release 8.0, including 128 bytes of on-chip tuple

memory.

Data Sheet

April 2005

™

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