74LCX573MTCX Fairchild Semiconductor, 74LCX573MTCX Datasheet - Page 6

IC LATCH OCT LV 5V I/O 20TSSOP

74LCX573MTCX

Manufacturer Part Number
74LCX573MTCX
Description
IC LATCH OCT LV 5V I/O 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX573MTCX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Circuits
8
Logic Family
74LC
Polarity
Non-Inverting
High Level Output Current
- 24 mA
Propagation Delay Time
9 ns at 2.7 V, 8 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX573MTCX
Manufacturer:
ST
0
Part Number:
74LCX573MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74LCX573MTCX-NL
Manufacturer:
LITELINK
Quantity:
4 613
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.0
AC Loading and Waveforms
CONTROL
CONTROL
OUTPUT
OUTPUT
Propagation Delay, Pulse Width and
DATA
DATA
OUT
CLOCK
3-STATE Output Low Enable and
IN
DATA
OUT
Waveform for Inverting and
IN
Non-Inverting Functions
Disable Times for Logic
t
t
PZL
rec
t
pxx
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t
t
Symbol
PHL
Waveforms
Figure 1. AC Test Circuit (C
SIGNAL
V
V
V
V
V
TEST
mo
V
mo
mi
t
x
y
W
mo
t
PLZ
t
pxx
t
V
rec
t
t
V
t
V
PZH
mi
V
PLH
DUT
PZL
V
mi
3.3V ± 0.3V
mi
CC
Test
mo
(Generic for LCX Family)
V
V
V
t
OH
, t
, t
, t
OL
mi
PLH
V
V
GND
mo
1.5V
1.5V
PHL
PLZ
PHZ
CC
V
V
+ 0.3V
– 0.3V
V
GND
V
GND
X
OL
CC
CC
C
L
V
L
CC
6V at V
includes probe and jig capacitance)
x 2 at V
500
6
500
V
V
Switch
CC
OL
OH
2.7V
Open
GND
V
1.5V
1.5V
CC
+ 0.3V
– 0.3V
CC
OUTPUT
3.3 ± 0.3V
CONTROL
ANY
CONTROL
2.5 ± 0.2V
OUTPUT
CLEAR
3-STATE Output High Enable and
INPUT
DATA
DATA
OUT
OPEN
GND
V
MR
OR
I
Setup Time, Hold Time and
IN
Recovery Time for Logic
Disable Times for Logic
2.5V ± 0.2V
t
t
V
r
10%
V
PZH
OH
OL
r
90%
V
V
t
= t
rise
CC
CC
+ 0.15V
– 0.15V
f
t
t
t
PLH
PZH
PZL
/ 2
/ 2
t
= 3ns)
and t
S
V
90%
mo
, t
, t
, t
t
PLZ
S
10%
PHL
t
PHZ
rec
V
fall
t
mi
PHZ
t
f
t
V
H
mi
V
mi
V
mi
www.fairchildsemi.com
V
V
V
GND
V
GND
V
GND
OH
Y
CC
CC
CC
V
V
OH
OL

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