PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

CaseN/ANotesNEW
Date_code11+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 52/164

Download datasheet (3Mb)Embed
PrevNext
PIC16F684
6.1
Timer1 Modes of Operation
Timer1 can operate in one of three modes:
• 16-bit Timer with prescaler
• 16-bit Synchronous counter
• 16-bit Asynchronous counter
In Timer mode, Timer1 is incremented on every instruc-
tion cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized
to
the
microcontroller
system
asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the Timer1 gate, which can be
selected as either the T1G pin or Comparator 2 output.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>)
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
FIGURE 6-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
DS41202C-page 50
6.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be the
clock
or
run
T1G pin or the output of Comparator 2. This allows the
device to directly time external events using T1G or
analog events using Comparator 2. See CMCON1
(Register 8-2) for selecting the Timer1 gate source.
This feature can simplify the software for a Delta-Sigma
A/D converter and many other applications. For more
information on Delta-Sigma A/D converters, see the
Microchip web site (www.microchip.com).
Note:
TMR1GE bit (T1CON<6>) must be set to
use either T1G or C2OUT as the Timer1
gate source. See Register 8-2 for more
information on selecting the Timer1 gate
source.
Timer1 gate can be inverted using the T1GINV bit
(T1CON<7>), whether it originates from the T1G pin or
Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
Preliminary
 2004 Microchip Technology Inc.