74AC573TTR STMicroelectronics, 74AC573TTR Datasheet

IC LATCH OCTAL D 3STATE 20-TSSOP

74AC573TTR

Manufacturer Part Number
74AC573TTR
Description
IC LATCH OCTAL D 3STATE 20-TSSOP
Manufacturer
STMicroelectronics
Series
74ACr
Datasheet

Specifications of 74AC573TTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 6 V
Independent Circuits
1
Delay Time - Propagation
4.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-7076-2
74AC573TTR

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Part Number:
74AC573TTR
Manufacturer:
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DESCRIPTION
The 74AC573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
CC
PLH
OH
NIH
CC
= 4 A(MAX.) at T
| = I
(OPR) = 2V to 6V
= V
t
PHL
OL
NIL
= 24mA (MIN)
= 28 % V
PD
= 4.5ns (TYP.) at V
A
CC
=25°C
(MIN.)
WITH 3 STATE OUTPUTS (NON INVERTED)
CC
2
= 5V
MOS
ORDER CODES
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched at the logic level of D input data. While the
(OE) input is low, the 8 outputs will be in a normal
logic state (high or low logic level); while OE is in
high level, the outputs will be in a high impedance
state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
OCTAL D-TYPE LATCH
74AC573M
74AC573B
TUBE
SOP
74AC573
74AC573MTR
74AC573TTR
TSSOP
T & R
1/11

Related parts for 74AC573TTR

74AC573TTR Summary of contents

Page 1

... high level, the outputs will high impedance 2 MOS state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC573 SOP TSSOP TUBE T & R 74AC573B 74AC573M 74AC573MTR 74AC573TTR 1/11 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE Don’t Care Z : High Impedance NOTE: Outputs are latched at the time when the input is taken LOW logic level LOGIC DIAGRAM This logic ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V (V) V High Level Input 3.0 IH Voltage 4.5 5.5 V Low Level Input 3.0 IL Voltage 4.5 5.5 V High Level Output 3.0 OH Voltage 4.5 5.5 3.0 4.5 5.5 V Low Level ...

Page 5

AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter V ( Propagation Delay 3.3 PLH PHL Time 5 Propagation Delay 3.3 PLH PHL Time 5 Output Enable 3.3 PZL PZH Time ...

Page 6

TEST CIRCUIT PLH PHL PZL PLZ PZH PHZ C = 50pF or equivalent (includes jig and probe capacitance 500 or equivalent ...

Page 7

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 74AC573 7/11 ...

Page 8

Plastic DIP-20 (0.25) MECHANICAL DATA DIM. MIN. a1 0.254 B 1. 8/11 mm TYP. MAX. MIN. 0.010 1.65 0.055 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 ...

Page 9

SO-20 MECHANICAL DATA mm DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. inch MAX. MIN. TYP. 2.65 0.20 0.004 2.45 ...

Page 10

DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 6.4 E 6. PIN 1 IDENTIFICATION 1 10/11 TSSOP20 MECHANICAL DATA mm TYP. MAX. 1.1 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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