74F533PC Fairchild Semiconductor, 74F533PC Datasheet

IC LATCH TRANSP OCT 3ST 20-DIP

74F533PC

Manufacturer Part Number
74F533PC
Description
IC LATCH TRANSP OCT 3ST 20-DIP
Manufacturer
Fairchild Semiconductor
Series
74Fr
Datasheet

Specifications of 74F533PC

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
6.7ns
Current - Output High, Low
3mA, 24mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74F533
© 2000 Fairchild Semiconductor Corporation
74F533SC
74F533SJ
74F533PC
74F533
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 74F533 is the same as the
74F373, except that the outputs are inverted.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
IEEE/IEC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009548
Features
Connection Diagram
Eight latches in a single package
3-STATE outputs for bus interfacing
Inverted version of the 74F373
Package Description
April 1988
Revised October 2000
www.fairchildsemi.com

Related parts for 74F533PC

74F533PC Summary of contents

Page 1

... Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F533SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Unit Loading/Fan Out Pin Names Description D –D Data Inputs Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) O –O Complementary 3-STATE Outputs 0 7 Function Table Inputs ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH PHL Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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