74ABT373CSJX Fairchild Semiconductor, 74ABT373CSJX Datasheet

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74ABT373CSJX

Manufacturer Part Number
74ABT373CSJX
Description
IC OCT TRANSP LATCH 3ST 20SOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet

Specifications of 74ABT373CSJX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
2.7ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT373CSJX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©1993 Fairchild Semiconductor Corporation
74ABT373 Rev. 1.4
74ABT373
Octal Transparent Latch with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
74ABT373CSC
74ABT373CSJ
74ABT373CMSA
74ABT373CMTC
Order Number
3-STATE outputs for bus interfacing
Output sink capability of 64mA, source capability of
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down
Nondestructive, hot-insertion capability
Package
Number
MSA20
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The ABT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup times is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH the
bus output is in the high impedance state.
Pin Descriptions
D
LE
OE
O
Pin Names
0
0
–D
–O
Package Description
7
7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-STATE Latch Outputs
Description
www.fairchildsemi.com
March 2007
tm

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74ABT373CSJX Summary of contents

Page 1

... MTC20 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 General Description The ABT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip- flops appear transparent to the data when Latch Enable (LE) is HIGH ...

Page 2

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Truth Table Inputs LE ...

Page 3

... Free Air Ambient Temperature A V Supply Voltage CC ∆ ∆ t Minimum Input Edge Rate Data Input Enable Input ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Parameter Parameter 3 Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V – ...

Page 4

... Outputs Enabled CCT I /Input CC Outputs 3-STATE Outputs 3-STATE I Dynamic I No Load CCD CC Notes: < 0.8mA/MHz. 2. For 8-bit toggling, I CCD 3. Guaranteed, but not tested. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 V Conditions CC Recognized HIGH Signal Recognized LOW Signal = –18mA Min –3mA Min –32mA I ...

Page 5

... SOIC and SSOP package. Symbol Parameter t Propagation Delay PLH PHL t Propagation Delay PLH PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Conditions = 50pF 25°C (4) 5 25°C (4) 5 (5) = 25°C 5 (6) = 25°C 5 (6) = 25° ...

Page 6

... LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded from the datasheet. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 = +25°C, = –55°C to +125°C, ...

Page 7

... This specification is guaranteed but not tested. Capacitance Symbol Parameter C Input Capacitance IN (16) C Output Capacitance OUT Note: is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. 16. C OUT ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 = –40°C to +85° 4.5V–5.5V 50pF (11) ...

Page 8

... Figure 1. Standard AC Test Load Amplitude 3.0V AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Figure 2. Test Input Signal Levels Rep. Rate t w 1MHz 500ns Figure 3 ...

Page 9

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Package Number M20B 9 www.fairchildsemi.com ...

Page 10

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Package Number M20D 10 www.fairchildsemi.com ...

Page 11

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Package Number MSA20 11 www.fairchildsemi.com ...

Page 12

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Package Number MTC20 12 www.fairchildsemi.com ...

Page 13

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ ...

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