MC74HC595ADR2G ON Semiconductor, MC74HC595ADR2G Datasheet - Page 7

• Manufacturer Part Number: MC74HC595ADR2G
• Description: IC SHIFT REGISTR 8BIT 3ST 16SOIC
• Manufacturer: ON Semiconductor
• Series: 74HCr
• Type: Not Requiredr

Specifications of MC74HC595ADR2G

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Serial to Parallel
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logic Family: HC
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC
• Propagation Delay Time: 225ns
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 16
• Counting Sequence: Serial to Serial/Parallel
• Number Of Circuits: 2
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2 V to 6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HC595ADR2GOS; MC74HC595ADR2GOS; MC74HC595ADR2GOSTR

OUTPUT
INPUT A
SWITCH
CLOCK
SERIAL
CLOCK
SHIFT
OUTPUTS
SQ
CLOCK
LATCH
Q
*Includes all probe and jig capacitance
H
A
-Q
H
10%
DEVICE
UNDER
50%
10%
90%
TEST
50%
10%
90%
50%
90%
50%
t
r
t
w
Figure 7.
t
PLH
t
t
50%
TLH
su
Figure 1.
Figure 3.
Figure 5.
1/f
t
PLH
OUTPUT
t
TLH
max
VALID
50%
TEST POINT
t
h
t
t
t
PHL
f
PHL
t
THL
t
THL
C
L
*
SWITCHING WAVEFORMS
V
GND
V
GND
CC
V
GND
V
GND
CC
CC
CC
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TEST CIRCUITS
7
OUTPUT Q
OUTPUT Q
DEVICE
OUTPUT
CLOCK
CLOCK
UNDER
ENABLE
LATCH
TEST
SHIFT
OUTPUT
CLOCK
RESET
SHIFT
SQ
H
*Includes all probe and jig capacitance
OUTPUT
50%
t
PHL
TEST POINT
50%
50%
t
t
50%
t
Figure 8.
PZL
PZH
su
Figure 2.
Figure 4.
Figure 6.
50%
C
1 kW
L
*
50%
t
t
t
w
50%
t
t
PHZ
w
rec
PLZ
50%
CONNECT TO V
TESTING t
CONNECT TO GND WHEN
TESTING t
10%
90%
PLZ
PHZ
AND t
AND t
CC
V
GND
V
GND
V
GND
HIGH
IMPEDANCE
V
V
HIGH
IMPEDANCE
CC
CC
CC
OL
OH
V
GND
V
GND
WHEN
PZL
PZH
CC
CC
.
.