M5M44260CTP-5 Mitsubishi, M5M44260CTP-5 Datasheet - Page 28

• Manufacturer Part Number: M5M44260CTP-5
• Description: FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
• Manufacturer: Mitsubishi

28
M5M44260CJ,TP-5,-5S : Under development
Note 28 : Self refresh sequence
Two refreshing methods should be used properly depending on
the low pulse width (t
period.
Table 2
RAS
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
(B) Definition of distributed refresh
Definition of CBR distributed refresh
(Including extended refresh)
Definition of RAS only distributed refresh
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
1.1 CBR distributed refresh
RAS
RAS only
distributed refresh
Read / Write Cycle
CBR distributed
refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within t
All combinations of nine row address signals (A
selected during 512 constant period (16µs max.) RAS only
refresh cycles within 8.2 ms.
The CBR distributed refresh performs more than 512
constant period (250µs max.) CBR cycles within 128 ms.
refresh
cycle
Read / Write Cycle
RASS
NSD
t
Read / Write
REF
refresh cycle
t
t
NSD
NSD
) of RAS signal during self refresh
Self Refresh
(shown in table 2).
/ 512
last
read/write
250µs
16µs
cycles
t
NSD
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh
t
t
SND
SND
Read / Write
refresh
cycle
250µs
16µs
0
Self Refresh Cycle
~A
t
RASS
8
t
) are
REF
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
100µs
1.2 RAS only distributed refresh
Switching from read/write operation to self refresh operation.
The time interval t
the last RAS only refresh cycle during read/write operation
period to the falling edge of RAS signal at the start of self
refresh operation should be set within 16µs.
Switching from self refresh operation to read/write operation.
The time interval t
the end of self refresh operation to the falling edge of RAS
signal in the first CBR refresh cycle during read/write
operation period should be set within 16µs.
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal
in the first CBR refresh cycle during read/write operation
period should be set within t
refresh
cycle
t
SND
t
REF
Read / Write Cycle
/ 512
NSD
SND
read/write
refresh cycle
cycles
from the falling edge of RAS signal in
from the rising edge of RAS signal at
first
SND
(shown in table 2).
MITSUBISHI LSIs