M5M4V16169DRT-15 Mitsubishi, M5M4V16169DRT-15 Datasheet

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... G# : Data I Power Supply Vcc : DQ Power Supply VccQ : Ground Vss :Address Fetch clock ADF# This pin can be None-Connect. :Must Connect Low MCL :Must Connect High MCH MITSUBISHI LSIs PINCONFIGURATION (TOP VIEW) Vss Vcc 70 1 Ad9 DQCl 69 2 Ad8 DQCu 68 3 Ad7 CC1# ...

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... Write Buffer 2 WB2 Write Buffer 1 WB1 WB1M S/A and I/O Col.Decoder 1Kx16=16K 1KBit SRAM SRAM Array MITSUBISHI LSIs VccQ RAS# (Row Address strobe) 30 CAS# (Column Address strobe) 31 DTD# (Data Transfer Direction) 8 CMd# Mask (Clock Mask for DRAM 16= ...

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... DRAM Row Decoder Ad0-11 8X16 1 of 4096 Decode RB1 Lower Byte Upper Byte DQ8-15 RB2 As0-2 Lower Byte Upper Byte Decode 16 bits 8X16 8X16 MITSUBISHI LSIs 8X16 Block As0-2 1of8Decode 16 bits DQs 16 bits 16 bits As0-2 1of8Decode (REV 1.0) Jul. 1998 3 ...

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... WB1 to DRAM.) Succeeding Buffer-Writes or Buffer Write Transfers will Clear Mask bits. 7) CMd# during current cycle must be High (see timing diagram for Auto-Refresh). 8) CMd# during current cycle must be Low (see timing diagram for Self-Refresh). MITSUBISHI LSIs DRAM Ad ( DRAM address ...

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... Function Data Transferred (max) WB2 --> RB 128 bits (8X16bit-block) DRAM --> RB 128 bits (8X16bit-block) RB --> Dout 8/16 bits RB --> SRAM 128 bits (8X16bit-block) MITSUBISHI LSIs No operation No operation No operation SRAM->DO DIN->SRAM RB2->SRAM SRAM->WB1 RB2->SRAM->DO DIN->SRAM->WB1 RB2->DO DIN->WB1 ...

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... When CMs# is asserted at a rising edge of K, the internal SRAM master clock for CMs# Input the following cycle is suspended, resulting in the power down of the SRAM portion of the circuit, including the Sense Amps. CMs# can also be used to retain output data during SRAM power-down. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 MITSUBISHI LSIs Ad0-Ad11 (@ (REV 1.0) Jul. 1998 6 ...

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... VccQ is the DQ power supply and allows the device to operate in a mixed voltage system (e.g., 5V data bus). As specified in the Table: Recommended Operating VccQ Supply Conditions, VccQ must be greater-than or equal-to the highest voltage experienced by the data bus. For 3.3V system operation, VccQ may be tied to Vcc. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 MITSUBISHI LSIs (REV 1.0) Jul. 1998 7 ...

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... DQ0-7 DQ8-15 Lower Byte Upper Byte 8X16 WB1 Lower Byte Upper Byte 8X16 8X16Block SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-9 1of4096Decode RB1 Upper Byte Lower Byte As0-2 1of8Decode RB2 16bits Upper Byte Lower Byte As0-2 1of8 Decode ...

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... DQ0-7 DQ8-15 Lower Byte Upper Byte 8X16 WB1 Upper Byte Lower Byte 8X16 8X16Block SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte Lower Byte As0-2 RB2 1of8Decode Lower Byte Upper Byte 16bits As0-2 1of8 Decode ...

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... Lower Byte Upper Byte 8X16 As0-2 1of8 Decode WB1 Lower Byte Upper Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte Lower Byte As0-2 1of8Decode RB2 16bits Lower Byte Upper Byte As0-2 1of8Decode 16bits ...

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... DQ0-7 DQ8-15 Lower Byte Upper Byte 8X16 As0-2 1of8 Decode WB1 Lower Byte Upper Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte As0-2 1of8Decode RB2 16bits Upper Byte DQs 16bits X 16bits 8X16 16bits ...

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... Lower Byte Upper Byte 8X16 Lower Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte As0-2 1of8Decode RB2 16bits Upper Byte DQs 16bits X 16bits 8X16 16bits ...

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... Lower Byte Upper Byte 8X16 Lower Byte As0-2 1of8 Decode WB1 Upper Byte Lower Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte As0-2 1of8Decode RB2 16bits Upper Byte DQs 16bits X 16bits 8X16 16bits ...

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... Lower Byte Upper Byte 8X16 Lower Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte As0-2 1of8Decode RB2 16bits Upper Byte DQs 16bits X 16bits 8X16 16bits ...

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... Lower Byte Upper Byte 8X16 Lower Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode RB1 Upper Byte Lower Byte As0-2 1of8Decode RB2 16bits Lower Byte Upper Byte DQs 16bits X ...

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... Lower Byte Upper Byte RB2 8X16 Lower Byte As0-2 1of8 Decode WB1 Upper Byte Lower Byte 8X16 SRAM 1KX16 SRAM RowDecoder As3-9 1of128Decode MITSUBISHI LSIs 8X16Block Ad0-11 1of4096Decode Upper Byte As0-2 1of8Decode 16bits Upper Byte DQs 16bits X 16bits 8X16 16bits As0-2 1of8Decode ...

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... Note that DNOP / DPD and DES / SPD or NOP command will be the stand-by command for the above power sequence. Vcc must be powered-on at the same time or before VccQ is on. And Vcc must be powered-off at the same time or after VccQ is off. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 MITSUBISHI LSIs (REV 1.0) Jul. 1998 17 ...

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... MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DQC G# tKHQZ Q DQ0-15 SR DES K DQC was deleted. G# tKLQZ Q DQ0-15 DES SR K DQC G# tKHQZ Q DQ0-15 MITSUBISHI LSIs DES SR SR tKHA tGLA Q tGLQ SR SR tKHA tKLA tGLA Q tGLQ tKHAR tKHQZ tGLA Q tGLQ (REV 1.0) Jul. 1998 tGHQ tGHQ ...

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... As0-9 DQ0-15 (Input) MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- CMDS t CSS DTS t CMSS t C0S t C1S DQCS t SADF MITSUBISHI LSIs t CMDH t CSH CMSH t C0H t C1H DQCH t HADF (REV 1.0) Jul. 1998 ...

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... DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Lower Upper Block address Column Block (16 byte mask, no write 1 : unmask, write enable MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- MITSUBISHI LSIs Upper DQs (REV 1.0) Jul. 1998 20 ...

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... Byte WB1/WB2 mask lower byte upper byte DWT2 DWT1 WM2 WB2 DWT1/DWT3 DWT2/DWT4 MITSUBISHI LSIs 1023 0 --- DRAM row 0 written 255 0 0 ->DQ15 addition DWT3/DWT4 DQ0-15 Load Byte Mask (LBM) DRAM (REV 1.0) Jul. 1998 21 ...

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... Color data is loaded from SRAM cache to WB1.(BWT) MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 DWT4 DNOP DWT4 DNOP DES DES DES Page call.(ACT) MITSUBISHI LSIs Window Boundary Page boundary DWT4 DNOP DWT4 PCG DES LBM DES DES Color data is transferred from WB2 to DRAM column block with new byte mask. ...

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... SRAM address and DRAM address can be multiplexed using this duration for DRAM control MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- Q1+1 Q1+3 Q1+2 Q2+1 SR DES MITSUBISHI LSIs Accept interrupt for inputting new address w/o gap Q3+3 Q3+1 Q3 (REV 1.0) Jul. 1998 ...

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... DES, SPD. "Insert wait" is possible. M5M4V16169D keeps compatibility setting ADF# low or setting Burst length=1 by SCR cycle. (Ad7, Ad8 and Ad9=0) MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- Q1+1 D1+2 DES SR SPD SPD DES SW SW MITSUBISHI LSIs ...

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... Input Capacitance, Clock pin I( Input Capacitance, I/O pin I/O MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 **-15 spec is the same as M5M4V16169TP/RT-15 Conditions With respect to Vss Parameter Supply Voltage Supply Voltage Test Condition V I f=1MHz =25mVrms V I MITSUBISHI LSIs Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 -65 ~ 150 Limits Min. Max Typ. 3.3 3.0 3 3.3 3.0 3 ...

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... L output open data input output open data input Parameter Test Condition IOH= -2mA IOL= 2mA Q floating VddQ+0. OUT MITSUBISHI LSIs Limits (MAX) -7 -10 -15 -8 260 200 140 240 150 160 130 100 140 ...

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... M5M4V16169TP/RT-15 (CLK pulse, input signals setup / hold time to CLK edge) VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL) Limits -7 -8 Max Min. Min. Max MITSUBISHI LSIs Unit -10 -15 Max Max Min. Min 3 ...

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... Min. Max Min. Max 10,000 10,000 49 56 100,000 100,000 MITSUBISHI LSIs Limits -10 -15 Min. Min. Max Max 120 90 120 10,000 12,000 60 70 100,000 100,000 20 20 ...

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... Output Active Time from G#-Low Edge tGHQ Output Disable Time from G#-High Edge MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 **-15 spec is the same as M5M4V16169TP/RT- Min. Max Min. Max 5.6 2 MITSUBISHI LSIs Limits -10 -15 Min. Min. Max Max 6 ...

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... As3 DQ0-15 D1 DES SW SR Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DES SW DES SW SR DRAM operation can be freely performed. MITSUBISHI LSIs SPD SPD SPD DES (REV 1.0) Jul. 1998 30 ...

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... DQ0-15 DES SR SW Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- SPD SPD DES SPD SR DRAM operation can be freely performed. MITSUBISHI LSIs DES SR SR (REV 1.0) Jul. 1998 31 ...

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... Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DES SW DES SW SR (l) (u) (l) DRAM operation can be freely performed. MITSUBISHI LSIs SPD SPD SPD DES ( (REV 1.0) Jul. 1998 14 32 ...

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... DQ0-15 D1 DES SW SR Note : Output is registered. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DRAM operation can be freely performed. MITSUBISHI LSIs SPD SPD DES DES (REV 1.0) Jul. 1998 14 33 ...

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... DQ0-15 DES SR BRT Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- (C1) (C1) (C1) (C5) (C5 BRTR DRAM operation can be freely performed. MITSUBISHI LSIs (C5) (C5 DES DES DES SR (REV 1.0) Jul. 1998 14 DES 34 ...

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... DQ0-15 DES BWT DES DES Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DES BWTW DES DES DRAM operation can be freely performed. MITSUBISHI LSIs BWT DES DES DES DES (REV 1.0) Jul. 1998 DES 35 ...

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... DQ0- Note : Output is transparent. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- DES DES DES BW DRAM operation can be freely performed. MITSUBISHI LSIs DES BR BR (REV 1.0) Jul. 1998 14 DES DES 36 ...

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... CC0# CC1# WE# DQC AS0-9 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CMd# RAS# DRAM operation can be freely performed. CAS# DTD# Ad0-11 MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- NO-Operation Mode MITSUBISHI LSIs (REV 1.0) Jul. 1998 37 ...

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... CAS# DTD# Ad0-11 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CMs# CC0# CC1# WE# SRAM operation can be freely performed. DQC(u/l) G# As0-9 DQ0-15 MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- NO-Operation Mode MITSUBISHI LSIs (REV 1.0) Jul. 1998 38 ...

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... DPD DPD DPD ACT CMs# CC0# CC1# WE# SRAM operation can be freely performed. DQC(u/l) G# As0-9 DQ0-15 DPD is recommended during no operation to save power. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- Row DNOP DNOP DNOP DNOP MITSUBISHI LSIs PCG DPD DPD DPD DPD (REV 1.0) Jul. 1998 39 ...

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... Ad0-11 DPD PCG DPD DPD ACT CMs# CC0# CC1# WE# SRAM operation can be freely performed. DQC(u/l) G# As0-9 DQ0-15 MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- tRC tRAS Row DNOP DNOP DNOP DNOP MITSUBISHI LSIs PCG DPD DPD DPD (REV 1.0) Jul. 1998 40 ...

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... M5M4V16169DTP/RT-7,-8,-10,- tRC DNOP DPD DPD DPD DPD DPD DPD ARF DRAM new commands except for NOP,DNOP and DPD can be set after tRC later from ARF command input. MITSUBISHI LSIs DNOP DNOP DNOP (REV 1.0) Jul. 1998 ...

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... Wait tRC for recovery d) Resume normal operation MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 4 Inhibit falling edge. H Halt Halt Self Refresh Mode SRAM Power Down Mode Self Refresh SRAM Power Down MITSUBISHI LSIs Row DNOP DNOP DNOP DNOP ACT tRC for Recovery Exit (REV 1 ...

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... Old Data Old Data PCG DPD DPD DPD ACT Old Old Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRAS tRSH Ad0-Ad2=Low **Col tCBF New Data Latency New Data DRT DPD DPD DPD ...

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... Old Data Old Data DPD DPD DPD DNOP ACT Old Old Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRSH Ad0-Ad2=Low **Col tCBF New Data Latency New Data DRT DPD DPD DPD DNOP ...

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... Old Data Old Data DPD DPD DPD ACT DNOP Old Old Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRSH Ad0-Ad2=Low **Col tCBF New Data Latency New Data DRT DPD DPD DPD DNOP ...

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... Old Data Old Data PCG DPD DPD DPD ACT DNOP Old Old Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRAS tRSH Ad0-Ad2=Low **Col tCBF New Data Latency New Data DRT DNOP PCG ...

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... Latency x t Latency DRT DNOP DRT DNOP DNOP Old Q1 Q2 Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tPC tPC tPC tRSH **C4 **C5 **C6 tCBF tCBF tCBF tCBF Latency Latency Latency ...

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... C1 C2 tCBF tCBF C1 DNOP DNOP DRT DNOP DRT Old Old Old Q1 ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRSH **C4 **C5 **C6 tCBF tCBF tCBF tCBF tCBF C2 DRT DRT DRT DRT DNOP BR ...

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... C1 Latency x t Latency DNOP DNOP DNOP DRT DRT Old Q1 Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tPC tRSH **C3 **C4 tCBF tCBF C2 C3 Latency DNOP DNOP DRT DRT DNOP BR BR ...

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... Ad0-Ad2=Low **C1 **C2 tCBF tCBF C1 Latency DRT DNOP DNOP DNOP DRT Old Old Old Old Old ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRSH **C3 tCBF C3 C2 Latency DRT DNOP DNOP DNOP PCG ...

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... Row Old Data PCG DPD DPD DPD ACT Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRAS tRWL Ad0-Ad2=Low **Col New Data[WB1(0-7 DWT1 DPD DPD DPD DNOP DNOP PCG BW BW ...

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... Row Row Old Data PCG DPD DPD DPD ACT MITSUBISHI LSIs tRAS tRWL Ad0-Ad2=Low **Col New Data[from WB1(0-7 DWT1 DPD DPD DPD DNOP DNOP PCG ...

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... Old Data Old Data DNOP DPD DPD DPD ACT Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRWL Ad0-Ad2=Low **Col New Data[WB1(0-7)] Next New Data New Data DNOP DWT1 DPD DPD DPD PCG BWT BWT SW ...

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... MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- tRC tRP tRCD Row Row Old Data PCG DPD DPD DPD ACT MITSUBISHI LSIs tRAS tRWL Ad0-Ad2=Low **Col New Data[from WB1(0-7 ...

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... Row Row Old Data PCG DPD DPD DPD ACT Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRASP tPC tRWL Ad0-Ad2=Low Ad0-Ad2=Low **Col **Col New Next Data[WB1(0-1)] Data[WB1(0-7 DWT1 DWT1 ...

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... Row Row Old Data DPD DPD ACT PCG DPD MITSUBISHI LSIs tRASP tPC tRWL Ad0-Ad2=Low Ad0-Ad2=Low **Col **Col Next Data[WB1(0-1)] New Data [from WB1(0-7 DNOP DNOP DNOP ...

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... PCG DPD DPD DPD ACT Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRAS tRWL Ad0=High Ad1-Ad2=Low **Col New Data[WB1(0-7 tCBF New Data[WB1(0-7)] Latency New Data[WB1(0-7)] ...

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... Row Row Old Data DPD DPD DPD ACT DNOP Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRASP tPC tRWL Ad1=High Ad0-Ad2=Low Ad0,Ad2=Low **Col **Col NoChange New Data[WB1(0-7 DNOP DNOP ...

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... Row Row Old Data DPD DPD DPD ACT DNOP Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). MITSUBISHI LSIs tRASP tPC tRWL Ad0,Ad1=High Ad0-Ad2=Low Ad2=Low **Col **Col NoChange New Data[WB1(0-7 tCBF New Data[WB1(0-7)] ...

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... BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM This page is left blank, so that the Set Command Register Timing Diagram on the next spread can be seen conveniently. MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,-15 MITSUBISHI LSIs 60 (REV 1.0) Jul. 1998 ...

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... DPD DPD DPD DPD DPD DPD MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- CMD SCR DPD DPD DPD ACT *Set Command Reg. Inhibit new command except for DNOP,DPD DES,SPD and NOP. MITSUBISHI LSIs Row DNOP DNOP DNOP (REV 1.0) Jul. 1998 61 ...

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... Inhibit new read or write function during these 4 clocks. MITSUBISHI LSIs Command Ad1 Ad0 operation Set All WB1 Xfer Masks L H Default Output ModeTransparent H L Output Mode Latched L L Output Mode Registered ...

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... MITSUBISHI LSIs Interleaved ...

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... MITSUBISHI ELECTRIC M5M4V16169DTP/RT-7,-8,-10,- +0.1 0.3 -0.05 +0.004 (0.012 ) -0.05 23.49+-0.1 (0.925+-0.004) 0.1 (0.004) Note) Dimension * not include mold flash. Dimension *3 does not include tie - bar cut remain. MITSUBISHI LSIs 36 0.5+-0.1 (0.02+-0.004) Detail (REV 1.0) Jul. 1998 A +0.05 0.125 -0.02 +0.02 ) (0.005 -0.0008 mm UNIT : (INCH) 64 ...