AM79C873KCW AMD [Advanced Micro Devices], AM79C873KCW Datasheet
AM79C873KCW
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AM79C873KCW Summary of contents
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PRELIMINARY Am79C873 NetPHY™ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS 100BASE-FX direct interface to industry standard electrical/optical transceivers 10/100BASE-TX physical-layer, single-chip transceiver Compliant with the IEEE 802.3u 100BASE-TX standard Compliant with the ANSI X3T12 ...
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BLOCK DIAGRAM 4B/5B Encoder MII MII Interface/ Signals Control 4B/5B Decoder Register 25M OSCI TX CGM NRZ Parallel NRZI to Scrambler to to Serial MLT-3 NRZI 25M CLK ...
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CONNECTION DIAGRAM FXSD- 2 FXSD+ 3 FXRD- 4 FXRD+ 5 AGND RXI- 9 RXI+ 10 AGND 11 AGND 12 13 10TXO- 10TXO AGND ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C873 K Valid Combinations Am79C873 KC ...
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RELATED AMD PRODUCTS Part No. Controllers Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™) Integrated Controllers Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet ...
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CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PIN DESCRIPTIONS MII Interface TX_ER/TXD4 Transmit Error In 100 Mbps mode, if this signal is asserted high and TX_EN is active, the HALT symbol is substituted for the actual data nibble Mbps mode, this input is ignored. In ...
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RX_EN Receive Enable This pin is active high enabled for receive signals RXD[3:0], RX_CLK, RX_DV and RX_ER. A low on this input tri-states these output pins. For normal operation in a NODE application, this pin should be pulled high. Media ...
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LNKSTS Link Status Register Bit This pin reflects the status of bit 2 register 1. OPMODE0-OPMODE3 OPMODE0-OPMODE3 These pins are used to control the forced or advertised operating mode of the NetPHY-1 device (see table be- low). The value is ...
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Clock Interface OSCI/X1 Crystal or Oscillator Input This pin should be connected MHz (±50 ppm) crystal if OSC/XTL MHz (±50 ppm) external TTL oscillator input, if OSC/XTLB=1. X2 Crystal Oscillator Output An external 25 ...
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FUNCTIONAL DESCRIPTION The NetPHY-1 Fast Ethernet single-chip transceiver, provides the functionality as specified in the IEEE 802.3u standard, integrates complete 100BASE-FX, 100BASE-TX modules and a complete 10BASE-T module. The NetPHY-1 device provides a Media Inde- pendent Interface (MII) as defined ...
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RX_DV (receive data valid) input from the PHY to in- dicate the PHY is presenting recovered and de- coded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconcilia- tion sublayer, RX_DV must encompass the ...
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Encoder MII MII Interface/ Signals Control Register Figure 3. 100BASE Transmitter Functional Block Diagram The block diagram in Figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following func- ...
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Table 1. 4B5B Code Group 4B code Symbol Meaning 3210 0 Data 0 0000 1 Data 1 0001 2 Data 2 0010 3 Data 3 0011 4 Data 4 0100 5 Data 5 0101 6 Data 6 0110 7 Data ...
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MLT-3 Driver The two binary data streams created at the MLT-3 con- verter are fed to the twisted pair output driver which converts these streams to current sources and alter- nately drives either side of the transmit transformer pri- mary ...
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Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. PECL Receiver The PECL receiver accepts PECL signal-level data from the FX ...
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This allows devices that do not support Auto-Negotiation but support a common mode of operation to establish a link. MII Serial Management The MII serial management interface consists of ...
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Register Description Register Address Register Name 0 BMCR 1 BMSR 2 PHYIDR1 3 PHYIDR2 4 ANAR 5 ANLPAR 6 ANER 16 DSCR 17 DSCSR 18 10BTCSR Others Reserved Key to Default In the register description that follows, the default col- ...
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Basic Mode Control Register (BMCR) - Register 0 Bit Bit Name 0.15 Reset 0, RW/SC 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power Down (PHYAD= 0.10 Isolate ...
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Basic Mode Control Register (BMCR) - Register 0 (Continued) Bit Bit Name Restart Auto- 0.9 0, RW/SC Negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6 Reserved Default Restart Auto-Negotiation: ...
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Basic Mode Status Register (BMSR) - Register 1 Bit Bit Name 1.15 100BASE-T4 100BASE-TX 1.14 Full Duplex 100BASE-TX 1.13 Half Duplex 10BASE-T 1.12 Full Duplex 10BASE-T 1.11 Half Duplex 1.10-1.7 Reserved MF Preamble 1.6 Suppression Auto-Negotiation 1.5 Complete 1.4 Remote ...
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Basic Mode Status Register (BMSR) - Register 1 Bit Bit Name Default 1.1 Jabber Detect Extended 1.0 Capability PHY ID Identifier Register 1 (PHYIDR1) - Register 2 The PHY Identifier Registers 1 and 2 work together in a single identifier ...
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Auto-Negotiation Advertisement Register(ANAR) - Register 4 This register contains the advertised abilities of the NetPHY-1 device as they will be transmitted to link partners dur- ing Auto-Negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12-4.11 Reserved 4.10 FCS ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner as they are received during Auto-Negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12-5.10 Reserved 5.9 T4 5.8 TX_FDX ...
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Auto-Negotiation Expansion Register (ANER) - Register 6 Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 6.2 NP_ABLE 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE Default Reserved: ...
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AMD Specified Configuration Register (DSCR) - Register 16 Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR Pin 97, RW 16.13 BP_ALIGN Pin 98, RW 16.12 Reserved 16.11 REPEATER Pin 94, RW 16.10 TX 16.9 UTP 16.8 CLK25MDIS 16.7 F_LINK_100 16.6 Reserved ...
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AMD Specified Configuration Register (DSCR) - Register 16 Bit Bit Name 16.5 LINKLED_CTL 16.4 FDXLED_MODE 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT Default LINKLED Mode Select: 0= ...
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AMD Specified Configuration and Status Register (DSCSR) - Register 17 Bit Bit Name 17.15 100FDX 17.14 100HDX 17.13 10FDX 17.12 10HDX 17.11- Reserved 17.10 17.8-17.4 PHYAD[4:0] (PHYAD), RW Bit Bit Name 17.3-17.0 ANMB[3: ...
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Configuration/Status (10BTCSRSCR) - Register 18 Bit Bit Name 18.15 Reserved 18.14 LP_EN Inverse Pin 94, 18.13 HBE 18.12 Reserved 18.11 JABEN 18.10 10BT_SER Pin 98, RW 18.9-18.1 Reserved 18.0 POLR ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC ELECTRICAL CHARACTERISTICS ( 70, unless specified otherwise) (Continued) ±5 Symbol Parameter MII TTL Outputs (RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO) V Output Low Voltage OL Output High ...
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AC ELECTRICAL CHARACTERISTICS (Over full range of operating conditions unless specified otherwise) (Continued) Symbol Parameter PECL Transmitter (FX Transmit Interface) pt 100FXTD+/- Differential Rise/Fall Time TR/F 100FXTD+/- Differential Rise/Fall Time pt TM Mismatch 100FXTD+/- Differential Output Duty pt TDC Cycle ...
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MII 100BASE-TX Transmit Timing TX_CLK tTX s TXD [0:3], TX_EN, TX_ER CRS 100TX Figure 7. MII 100BASE-TX Transmit Timing Diagram MII 100BASE-TX Transmit Timing Parameters (Half Duplex) Symbol Parameter TXD[0:3], TX_EN, TX_ER Setup To tTX s TX_CLK High TXD[0:3], TX_EN, ...
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MII 100BASE-TX Receive Timing RX_CLK RXD [0:3], RX_DV, RX_ER CRS t 3 RXI COL Figure 8. MII 100BASE-TX Receive Timing Diagram MII-100BASE-TX Receive Timing Parameter (Half Duplex) Symbol Parameter RXD[0:3), RX_DV, RX_ER Setup To tRX s RX_CLK High RXD[0:3], RX_DV, ...
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Auto-Negotiation and Fast Link Pulse Timing Clock Pulse Fast Link Pulses FLP Burst 10TX0 Figure 9. Auto-Negotiation and Fast Link Pulse Timing Diagram Auto-Negotiation and Fast Link Pulse Timing Parameters Symbol Parameter t1 Clock/Data Pulse Width t2 Clock Pulse To ...
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MII 10BASE-T Receive Nibble Timing Diagram RX_CLK tTX RXD [0:3], RX_DV, RX_ER CRS t 3 RXI± Figure 11. MII 10BASE-T Receive Nibble Timing Diagram MII-10BASE-T Receive Nibble Timing Parameters Symbol Parameter RXD[0:3), RX_DV, RX_ER Setup To tRX s RX_CLK High ...
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SQE (Heartbeat) Timing TX_CLK TX_EN COL Figure 12. 10BASE-T SQE (Heartbeat) Timing Diagram 10BASE-T SQE (Heartbeat) Timing Parameters Symbol Parameter t1 COL (SQE) Delay After TX_EN Off t2 COL (SQE) Pulse Duration 10BASE-T Jab and Unjab Timing TX_EN TDX ...
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MDIO Timing when OUTPUT by STA MDC MDIO Figure 14. MDIO Timing when OUTPUT by STA Timing Diagram MDIO Timing when OUTPUT by NetPHY-1 Device MDC MDIO Figure 15. MDIO Timing when OUTPUT by NetPHY-1 Timing Diagram MII Timing Parameters ...
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MAGNETICS SELECTION GUIDE The NetPHY-1 device requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of mag- netic manufacturers. Designers should ...
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Table 3. Part List for Example Design Item No Qty Reference Number 1 11 C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C13 2 1 C12 3 4 D1,D2,D3, L1, OSC1 7 2 Q2, R1, ...
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NetPHY-1 MII Example Schematic VCC VCC R9 10K C1 10u GND S1 SW SPST 81 RESET# TMODE 82 TESTMODE PHAD0 83 PHYAD0 PHAD1 84 PHYAD1 PHAD2 85 PHYAD2 GND 86 DGND VCC 87 DVCC PHAD3 88 PHYAD3 PHAD4 89 PHYAD4 ...
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NetPHY-1 MII Example Schematic (Continued) D1 TXLED D2 RXLED LED D3 LILED LED D4 COLLED LED D5 FDXLED LED LED D6 CLK25M D7 SD LED D8 RXLOCK LED D9 SPEED LED D10 SIGOK LED LED VCC BYPASS CAPACITOR FOR U1 ...
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PHYSICAL DIMENSIONS* PQR100 HD D 100 See Detail F Seating Plane *For Reference Only Dimensions Symbol Dimensions Inches A 0.130 Max. A1 0.004 Min. A2 0.1120.005 b 0.012 +0.004 -0.002 c ...