AM79C901AJCT AMD [Advanced Micro Devices], AM79C901AJCT Datasheet - Page 63

• Manufacturer Part Number: AM79C901AJCT
• Description: HomePHY Single-Chip 1/10 Mbps Home Networking PHY
• Manufacturer: AMD [Advanced Micro Devices]

TBR16: 10BASE-T Status and Enable Register (Register 16)
The status bits indicate when there is a change in the
Link Status, Duplex Mode, Auto-Negotiation status,
or Speed status. Register 16 contains the status and
enable bits. The status is always updated whether or
Note:
All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.
15:14
Bits
7:5
13
12
11
10
9
8
4
3
2
1
0
Auto-Negotiation Change
Auto-Negotiation Change
Speed Change Enable
Duplex Mode Change
Duplex Mode Change
Link Status Change
Link Status Change
Status Test Enable
Speed Change
Global Enable
Reserved
Reserved
(Note 1)
Enable
Enable
Enable
Global
Name
Table 50. TBR16: 10BASE-T Status and Enable Register (Register 16)
1 = When this bit is set, setting bits 12:9 of this register
0 = Bits 4:1 are only set if the interrupt condition (if any
1 = Link Status change enable
0 = This interrupt is masked
1 = Duplex Mode change enable
0 = This interrupt is masked
1 = Auto-Negotiation change enable
0 = This interrupt is masked
1 = Speed change enable
0 = This interrupt is masked
1= Global interrupt enable
0 = This interrupt is masked
1 = Link Status has changed on a port
0 = No change in Link Status
1 = Duplex Mode has changed on a port
0 = No change in Duplex mode
1 = Auto-Negotiation status has changed on a port
0 = No change in Auto-Negotiation status
1 = Speed status has changed on a port
0 = No change
1 = Indicates a change in status of any of the above
interrupts
0 = Indicates no change in Interrupt status
will cause a condition that will set bits 4:1
accordingly. The effect is to test the register bits with
a forced interrupt condition.
bits in 12:9 are set) occurs.
P R E L I M I N A R Y
Am79C901A
Description
not the enable bits are set. When a status change oc-
curs, the system will need to read this register to
clear the status bits. See Table 50.
Read/
Write
R, LH
R, LH
R, LH
R, LH
R, LH
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Default Value
(hex)
0
0
0
0
0
0
0
0
0
0
0
0
0
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