AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 5

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

ALE can be used by a Slave device to control a latch on
the bus address lines. When ALE is HIGH, the latch is
open, and when ALE goes LOW, the latch is closed.
As AS (CSR3 (01), ACON = 1), the signal pulses LOW
PIN DESCRIPTION
A16–A23
High Order Address Bus (Output, Three-State)
Additional address bits to access a 24-bit address.
These lines are driven as a Bus Master only.
ADR
Register Address Port Select (Input)
When the C-LANCE is a Slave, ADR indicates which of
the two register ports is selected. ADR LOW selects
register data port; ADR HIGH selects register address
port. ADR must be valid throughout the data portion of
the bus cycle and is only used by the C-LANCE when
CS is LOW.
ALE/AS
Address Latch Enable (Output, Three-State)
Used to demultiplex the DAL lines and define the
address portion of the bus cycle. This l/O pin is pro-
grammable through bit (01) of CSR3.
As ALE (CSR3 (01), ACON = 0), the signal transitions
from a HIGH to a LOW during the address portion of
the transfer and remains LOW during the data portion.
during the address portion of the bus transaction. The
LOW-to-HlGH transition of AS can be used by a Slave
device to strobe the address into a register.
The C-LANCE drives the ALE/AS line only as a Bus
Master.
BM0/BYTE, BM
(Output, Three-State)
The two pins are programmable through bit (00) of
CSR3.
BM0, BM1—If CSR3 (00) BCON = 0
PIN 15 = BM0 (Output, Three-State) (48-Pin DlPs)
PIN 16 = BM1 (Output, Three-State) (48-Pin DlPs)
BM0, BM1 (Byte Mask). This indicates that the byte(s)
on the DAL are to be read or written during this bus
transaction. The C-LANCE drives these lines only as a
Bus Master. It ignores the Byte Mask lines when it is a
Bus Slave and assumes word transfers.
1
/BUSAKO
P R E L I M I N A R Y
Am79C90
Byte selection using Byte Mask is done as described
by the following table:
BYTE, BUSAKO—If CSR3 (00) BCON = 1
PIN 15 = BYTE (Output, Three-State) (48-Pin DlPs)
PIN 16 = BUSAKO (Output) (48-Pin DIPs)
Byte selection may also be done using the BYTE line
and DAL00 line, latched during the address portion of
the bus cycle. The C-LANCE drives BYTE only as a
Bus Master and ignores it when a Bus Slave selection
is done (similar to BM0, BM1). Byte selection is done
as outlined in the following table:
BUSAKO is a bus request daisy chain output. If the chip
is not requesting the bus and it receives HLDA,
BUSAKO will be driven LOW. If the C-LANCE is re-
questing the bus when it receives HLDA, BUSAKO will
remain HIGH.
Byte Swapping
In order to be compatible with the variety of 16-bit mi-
croprocessors available to the designer, the C-LANCE
may be programmed to swap the position of the upper-
and lower-order bytes on data involved in transfers with
the internal FIFOs.
Byte swapping is done when BSWP = 1. The most
significant byte of the word in this case will appear on
DAL lines 7–0 and the least significant byte on DAL
lines 15–8.
When BYTE = H (indicating a byte transfer) the table in-
dicates on which part of the 16-bit data bus the actual
data will appear.
Whenever byte swap is activated, the only data that is
swapped is data traveling to and from the Transmit/
Receive FIFOs.
BYTE
HlGH
HlGH
HlGH
HlGH
LOW
LOW
LOW
LOW
BM
1
DAL
HIGH
HIGH
HIGH
HIGH
BM
LOW
LOW
LOW
LOW
00
0
Selection
Whole Word
Upper Byte
Lower Byte
None
Selection
Whole Word
Illegal Condition
Lower Byte
Upper Byte
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