SI5316-C-GMR Silicon Laboratories Inc, SI5316-C-GMR Datasheet

SI5316-C-GMR

Manufacturer Part Number

SI5316-C-GMR

Description

QFN 36/-40 TO 85 OC/PRECISION CLOCK JITTER ATTENUATOR, 1 OUTPUT, PIN CONTRO

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5316-C-GMR.pdf (16 pages)

Specifications of SI5316-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

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Description

The Si5316 is a low jitter, precision jitter attenuator for

high-speed communication systems, including OC-48,

OC-192, 10G Ethernet, and 10G Fibre Channel. The

Si5316 accepts dual clock inputs in the 19, 38, 77, 155,

311, or 622 MHz frequency range and generates a

jitter-attenuated clock output at the same frequency.

Within each of these clock ranges, the device can be

tuned

SONET/SDH frequencies, up to a maximum of

710 MHz in the 622 MHz range. The Si5316 is based

technology,

synthesis and jitter attenuation in a highly integrated

PLL solution that eliminates the need for external

VCXO and loop filter components. The DSPLL loop

bandwidth is digitally programmable, providing jitter

performance optimization at the application level.

Operating from a single 1.8, 2.5, or 3.3 V supply, the

Si5316 is ideal for providing jitter attenuation in high

performance timing applications.

Applications

Rev. 0.4 4/08

Loss of Signal

RECISION

Optical modules

SONET/SDH OC-48/OC-192/STM-16/STM-64 line

cards

10GbE, 10GFC line cards

ITU G.709 line cards

Wireless basestations

Silicon

CK1DIV

CK2DIV

CKIN1

CKIN2

approximately

Laboratories'

which

Signal

Detect

provides

15%

L O C K

3rd-generation

higher

Xtal or Refclock

Select

Clock

any-rate

than

Frequency

I T T E R

Select

frequency

DSPLL

nominal

DSPLL

Bandwidth

Select

TTENUATOR

Features

Test and measurement

Synchronous Ethernet

Fixed frequency jitter attenuator with selectable

clock ranges at 19, 38, 77, 155, 311, and 622 MHz

(710 MHz max)

Support for SONET, 10GbE, 10GFC, and

corresponding FEC rates

Ultra-low jitter clock output with jitter generation as

low as 0.3 ps

Integrated loop filter with selectable loop bandwidth

(100 Hz to 7.9 kHz)

Meets OC-192 GR-253-CORE jitter specifications

Dual clock inputs with integrated clock select mux

One clock input can be 1x, 4x, or 32x the frequency

of the second clock input

Single clock output with selectable signal format:

LVPECL, LVDS, CML, CMOS

LOL, LOS alarm outputs

Pin programmable settings

On-chip voltage regulator for 1.8 ±5%, 2.5 ±10%, or

3.3 V ±10% operation

Small size (6 x 6 mm 36-lead QFN)

Pb-free, RoHS compliant

Loss of

Lock

Bypass

PLL

RMS

(50 kHz–80 MHz)

Si5316

Signal Format

CKOUT

Disable

VDD (1.8, 2.5, or 3.3 V)

GND

Si5316

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