SI5317D-C-GMR Silicon Laboratories Inc, SI5317D-C-GMR Datasheet

SI5317D-C-GMR

Manufacturer Part Number

SI5317D-C-GMR

Description

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5317D-C-GMR.pdf (46 pages)

Specifications of SI5317D-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

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Features



Applications



Description

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications

that require jitter attenuation without clock multiplication. The Si5317 accepts a

single clock input ranging from 1 to 711 MHz and generates two low jitter clock

outputs at the same frequency. The clock frequency range and loop bandwidth are

selectable from a simple look-up table. The Si5317 is based on Silicon

Laboratories' 3rd-generation DSPLL

on any frequency in a highly integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The DSPLL loop bandwidth is user

selectable, providing jitter performance optimization at the application level.

Functional Block Diagram

Rev. 1.1 4/11

Clock In

I N

Provides jitter attenuation for any clock

frequency

One clock input / two clock outputs

Input/output frequency range:

1–711 MHz

Ultra low jitter: 300 fs

(12 kHz–20 MHz) typical

Simple pin control interface

Selectable loop bandwidth for jitter

attenuation: 60 Hz–8.4 kHz

Meets OC-192 GR-253-CORE jitter

specifications

Data converter clocking

Wireless infrastructure

Networking, SONET/SDH

Frequency Select [3:0]

Bandwidth Select [1:0]

Phase Skew INC/DEC

- C

Frequency Table

ONTR OLLED

Status/Control

XTAL/Clock

DSPLL

technology, which provides jitter attenuation

1 – 7 11 M H



Loss of Lock

Loss of Signal

XTAL/Clock Rate [1:0]

Selectable output clock signal

format: LVPECL, LVDS, CML or

CMOS

Single supply: 1.8, 2.5, or 3.3 V

Loss of lock and loss of signal

alarms

VCO freeze during LOS/LOL

On-chip voltage regulator with high

PSRR

Small size: 6 x 6 mm, 36-QFN

Wide temperature range: –40 to

+85 ºC

Switches and routers

Medical instrumentation

Test and measurement

Regulator

PSRR

High

GND

Clock Out2

VDD (1.8, 2.5, 3.3 V)

Clock Out1

Signal Format [1:0]

I T T E R

FRQTBL

LEANING

GND

VDD

RST

LOS

Ordering Information:

10 11 12 13 14 15 16 17

Pin Assignments

See page 40.

Si5317

GND

Pad

L O C K

Si5317

FRQSEL3

FRQSEL2

FRQSEL1

FRQSEL0

BWSEL1

BWSEL0

INC

DEC

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