SI5323-C-GMR Silicon Laboratories Inc, SI5323-C-GMR Datasheet

SI5323-C-GMR

Manufacturer Part Number

SI5323-C-GMR

Description

QFN 36/-40 TO 85 OC/PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTE

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5323-C-GMR.pdf (40 pages)

Specifications of SI5323-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

Current page: 1 of 40
Download datasheet (383Kb)

Features



Applications



Description

The Si5323 is a jitter-attenuating precision clock multiplier for high-speed

communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre

Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz

and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to

1050 MHz. The input clock frequency and clock multiplication ratio are selectable

from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is

based on Silicon Laboratories' 3rd-generation DSPLL

provides any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and loop filter components.

The DSPLL loop bandwidth is digitally programmable, providing jitter performance

optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V

supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in

high performance timing applications.

Functional Block Diagram

Rev. 1.0 1/11

Loss of Signal

Loss of Lock

I N

Pin-selectable output frequencies

ranging from 8 kHz–708 MHz

Ultra-low jitter clock outputs as low

as 250 fs rms (12 kHz–20 MHz)

270 fs rms (50 kHz–80 MHz)

Integrated loop filter with selectable

loop bandwidth (60 Hz–8.4 kHz)

Meets ITU-T G.8251 and Telcordia

OC-192 GR-253-CORE jitter

specifications

Hitless input clock switching with

phase build-out and digital hold

SONET/SDH OC-48/STM-16 and

OC-192/STM-64 line cards

GbE/10GbE, 1/2/4/8/10GFC line cards

ULTIPLIER

CKIN1

CKIN2

- P

ROGRAMMABLE

Signal Detect

Bandwidth Select

Frequency Select

Xtal or Refclock

Rate Select

I T T E R

DSPLL

Control



Dual clock outputs with selectable

signal format (LVPECL, LVDS, CML,

CMOS)

Support for ITU G.709 FEC ratios

(255/238, 255/237, 255/236)

LOL, LOS alarm outputs

Pin-controlled output phase adjust

Single supply 1.8 ±5%, 2.5 or 3.3 V

±10% operation with high PSRR

On-chip voltage regulator

Small size: 6 x 6 mm 36-lead QFN



Clock Select

Manual/Auto Switch

Skew Control

ITU G.709 line cards

Optical modules

Test and measurement

Synchronous Ethernet

TTENUA TOR

R E C I S I O N

technology, which

CKOUT1

Signal Format

Disable/BYPASS

CKOUT2

VDD (1.8, 2.5, or 3.3 V)

GND

LOCK

AUTOSEL

FRQTBL

GND

VDD

RST

C1B

C2B

Ordering Information:

Pin Assignments

10 11 12 13 14 15 16 17

See page 33.

Si5323

GND

Pad

FRQSEL3

FRQSEL2

FRQSEL1

FRQSEL0

BWSEL1

BWSEL0

CS_CA

INC

DEC

Si5323

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