SI5325A-C-GMR Silicon Laboratories Inc, SI5325A-C-GMR Datasheet

SI5325A-C-GMR

Manufacturer Part Number

SI5325A-C-GMR

Description

QFN 36/-40 TO 85 OC/MP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER, 2 OUTPUTS(1

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5325A-C-GMR.pdf (62 pages)

Specifications of SI5325A-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

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µ P - P

Features



Applications



Description

The Si5325 is a low jitter, precision clock multiplier for applications requiring clock

multiplication without jitter attenuation. The Si5325 accepts dual clock inputs

ranging from 10 to 710 MHz and generates two clock outputs ranging from 2 kHz

to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down

separately from a common source. The device provides frequency translation

combinations across this operating range. The Si5325 input clock frequency and

clock multiplication ratio are programmable through an I

Si5325 is based on Silicon Laboratories' 3rd-generation DSPLL

which provides frequency synthesis in a highly integrated PLL solution that

eliminates the need for external VCXO and loop filter components. The DSPLL

loop bandwidth is digitally programmable. Operating from a single 1.8, 2.5, or

3.3 V supply, the Si5325 is ideal for providing clock multiplication in high

performance timing applications

Rev. 0.5 2/12

Not recommended for new

designs. For alternatives, see the

Si533x family of products.

Generates frequencies from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an

input frequency of 10 to 710 MHz

Low jitter clock outputs with jitter

generation as low as 0.5 ps rms

(12 kHz–20 MHz)

Integrated loop filter with

selectable loop bandwidth

(150 kHz to 2 MHz)

Dual clock inputs w/manual or

automatically controlled

switching

SONET/SDH OC-48/STM-16 and

OC-192/STM-64

line cards

GbE/10GbE, 1/2/4/8/10GFC line

cards

ITU G.709 and custom FEC line

cards

ROGRAMMABLE



Dual clock outputs with

selectable signal format

(LVPECL, LVDS, CML, CMOS)

Support for ITU G.709 and

custom FEC ratios (255/238,

255/237, 255/236)

LOS, FOS alarm outputs

On-chip voltage regulator for

1.8 ±5%, 2.5 or 3.3 V ±10%

operation

Small size: 6 x 6 mm 36-lead

QFN

Pb-free, ROHS compliant

Optical modules

Wireless basestations

Data converter clocking

xDSL

SONET/SDH + PDH clock synthesis

Test and measurement

C or SPI programmable

RECISION

C or SPI interface. The

technology,

L O C K

INT_C1B

GND

VDD

RST

C2B

Ordering Information:

ULTIPLIER

10 11 12 13 14 15 16 17

Pin Assignments

See page 56.

Si5325

GND

Pad

Si5325

SDI

A2_SS

SDA_SDO

SCL

CS_CA

GND

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