SI5326A-C-GMR Silicon Laboratories Inc, SI5326A-C-GMR Datasheet

SI5326A-C-GMR

Manufacturer Part Number

SI5326A-C-GMR

Description

QFN 36/-40 TO 85 OC/ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5326C-C-GMR.pdf (72 pages)

Specifications of SI5326A-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

SI5326A-C-GMR

Manufacturer:

SILICON LABS/芯科

Quantity:

20 000

Current page: 1 of 72
Download datasheet (376Kb)

Features



Applications



Description

The Si5326 is a jitter-attenuating precision clock multiplier for applications

requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to

945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down

separately from a common source. The Si5326 can also use its crystal oscillator

as a clock source for frequency synthesis. The device provides virtually any

frequency translation combination across this operating range. The Si5326 input

clock frequency and clock multiplication ratio are programmable through an I

SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation

DSPLL

highly integrated PLL solution that eliminates the need for external VCXO and

loop filter components. The DSPLL loop bandwidth is digitally programmable,

providing jitter performance optimization at the application level. Operating from a

single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock

multiplication and jitter attenuation in high performance timing applications.

Rev. 1.0 9/10

N Y

T T E N U A T O R

Generates any frequency from 2 kHz

to 945 MHz and select frequencies to

1.4 GHz from an input frequency of

2 kHz to 710 MHz

Ultra-low jitter clock outputs with jitter

generation as low as 0.3 ps rms

(50 kHz–80 MHz)

Integrated loop filter with selectable

loop bandwidth (60 Hz to 8.4 kHz)

Meets OC-192 GR-253-CORE jitter

specifications

Dual clock inputs with manual or

automatically controlled hitless

switching (LVPECL, LVDS, CML,

CMOS)

SONET/SDH OC-48/OC-192/STM-

16/STM-64 line cards

ITU G.709 and custom FEC line

cards

GbE/10GbE, 1/2/4/8/10G Fibre

Channel line cards

GbE/10GbE Synchronous Ethernet

technology, which provides frequency synthesis and jitter attenuation in a

R E Q UE N C Y

R E C I S I O N



Dual clock outputs with selectable

signal format

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236)

LOL, LOS, FOS alarm outputs

Digitally-controlled output phase

adjustment

On-chip voltage regulator for

1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%

operation

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS compliant

Optical modules

Wireless basestations

Data converter clocking

xDSL

PDH clock synthesis

Test and measurement

Broadcast video

C or SPI programmable

L O C K

C or

U L T I P L I E R

INT_C1B

GND

VDD

RST

C2B

Ordering Information:

Pin Assignments

10 11 12 13 14 15 16 17

/ J

See page 65.

Si5326

I T T E R

GND

Pad

SDI

A2_SS

SDA_SDO

SCL

CS_CA

INC

DEC

Si5326

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