C8051F040GQ Silicon Laboratories Inc, C8051F040GQ Datasheet
C8051F040GQ
Manufacturer Part Number
C8051F040GQ
Description
TQFP-100
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F040GQ.pdf
(326 pages)
Specifications of C8051F040GQ
Date_code
09+
- Current page: 1 of 326
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Rev. 1.5 12/05
Analog Peripherals
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On-Chip JTAG Debug & Boundary Scan
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10 or 12-Bit SAR ADC
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8-bit SAR ADC (C8051F040/1/2/3 only)
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Two 12-bit DACs (C8051F040/1/2/3 only)
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Three Analog Comparators
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Voltage Reference
Precision V
On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
± 1 LSB INL, guaranteed no missing codes
Programmable throughput up to 100 ksps
13 External Inputs; single-ended or differential
SW programmable high voltage difference amplifier
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
Programmable throughput up to 500 ksps
8 External Inputs, single-ended or differential
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free wave-
form generation
Programmable hysteresis/response time
DD
Monitor/Brown-Out Detector
C8051F041/2/3
ANALOG PERIPHERALS
12-Bit
INTERRUPTS
DAC
ONLY
Copyright © 2005 by Silicon Laboratories
8051 CPU
(25 MIPS)
PGA
20
12-Bit
HIGH-SPEED CONTROLLER CORE
DAC
VREF
SENSOR
PGA
500 ksps
TEMP
VOLTAGE COMPARATORS
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ADC
8-bit
CIRCUITRY
DEBUG
100 ksps
12/10-bit
64 kB/32 kB
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ISP FLASH
ADC
DIFF
AMP
HV
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High-Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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Supply Voltage: 2.7 to 3.6 V
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100-Pin and 64-Pin TQFP Packages Available
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C8051F040/1/2/3/4/5/6/7
CIRCUIT
CLOCK
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
20 vectored interrupt sources
4352 bytes internal data RAM (4 k + 256)
64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system program-
mable in 512-byte sectors
External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watch-dog timer; bi-directional reset pin
Internal calibrated programmable oscillator: 3 to
24.5 MHz
External oscillator: crystal, RC, C, or clock
Real-time clock mode using Timer 2, 3, 4, or PCA
Multiple power saving sleep and shutdown modes
Temperature Range: –40 to +85 °C
SPI Bus
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
UART0
UART1
SMBus
Mixed Signal ISP Flash MCU Family
CAN
2.0B
PCA
4352 B
SRAM
DIGITAL I/O
64 pin
CONTROL
SANITY
JTAG
100 pin
Port 4
Port 5
Port 6
Port 7
Port 0
Port 1
Port 2
Port 3
2
C™ Compatible), SPI™, and
C8051F04x
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