C8051F120GQ Silicon Laboratories Inc, C8051F120GQ Datasheet
C8051F120GQ
Manufacturer Part Number
C8051F120GQ
Description
TQPF100
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F120GQ.pdf
(350 pages)
Specifications of C8051F120GQ
Date_code
09+
- Current page: 1 of 350
- Download datasheet (3Mb)
Preliminary Rev. 1.4 12/05
Analog Peripherals
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On-Chip JTAG Debug & Boundary Scan
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100-Pin TQFP or 64-Pin TQFP Packaging
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10 or 12-bit SAR ADC
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8-bit SAR ADC (‘F12x Only)
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Two 12-bit DACs (‘F12x Only)
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Two Analog Comparators
Voltage Reference
V
On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
Temperature Range: –40 to +85 °C
RoHS Available
DD
± 1 LSB INL
Programmable throughput up to 100 ksps
Up to 8 external inputs; programmable as single-
ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
Programmable throughput up to 500 ksps
8 external inputs (single-ended or differential)
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free wave-
form generation
Monitor/Brown-Out Detector
(5 0 o r 1 0 0 M IP S )
A N A L O G P E R IP H E R A L S
IN T E R R U P T S
Copyright © 2005 by Silicon Laboratories
8 0 5 1 C P U
C 8 0 5 1 F 1 2 x O n ly
2 0
C O M P A R A T O R S
P G A
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H IG H -S P E E D C O N T R O L L E R C O R E
V O L T A G E
P G A
V R E F
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5 0 0 k s p s
IS P F L A S H
C IR C U IT R Y
A D C
1 2 8 /6 4 k B
8 -b it
D E B U G
1 0 /1 2 -b it
1 0 0 k s p s
S E N S O R
T E M P
A D C
1 2 -B it
1 2 -B it
D A C
D A C
8 4 4 8 B
S R A M
High Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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Voltage Supples
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C L O C K / P L L
C8051F120/1/2/3/4/5/6/7
C IR C U IT
S P I B u s
U A R T 0
U A R T 1
T im e r 0
T im e r 1
T im e r 2
T im e r 3
T im e r 4
S M B u s
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
100 MIPS or 50 MIPS throughput with on-chip PLL
2-cycle 16 x 16 MAC engine (C8051F120/1/2/3 and
C8051F130/1/2/3 only)
8448 bytes internal data RAM (8 k + 256)
128 or 64 kB Banked Flash; in-system programma-
ble in 1024-byte sectors
External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
8 byte-wide port I/O (100TQFP); 5 V tolerant
4 Byte-wide port I/O (64TQFP); 5 V tolerant
Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
Internal precision oscillator: 24.5 MHz
Flexible PLL technology
External Oscillator: Crystal, RC, C, or clock
Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
Power saving sleep and shutdown modes
P C A
Mixed Signal ISP Flash MCU Family
('F 1 2 0 /1 /2 /3 , 'F 1 3 x )
D IG IT A L I/O
1 6 x 1 6 M A C
6 4 p in
J T A G
1 0 0 p in
C8051F130/1/2/3
P o r t 4
P o r t 5
P o r t 6
P o r t 7
P o rt 0
P o rt 1
P o rt 2
P o rt 3
C8051F12x C8051F13x
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