M5M44260CJ-7 Mitsumi Electronics, Corp., M5M44260CJ-7 Datasheet

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M5M44260CJ-7

Manufacturer Part Number
M5M44260CJ-7
Description
Manufacturer
Mitsumi Electronics, Corp.
Datasheet

Specifications of M5M44260CJ-7

Case
SOJ-40
Date_code
1997+

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1
M5M44260CJ,TP-5,-5S : Under development
DESCRIPTION
Microcomputer memory, Refresh memory for CRT
FEATURES
PIN DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
512 cycles every 8.2ms.
XX=J,TP
APPLICATION
The use of double-layer metalization process technology and a
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability *
Extended refresh capability
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
This device has 2CAS and 1W terminals with a refresh cycle of
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
DQ
RAS
LCAS
UCAS
W
OE
V
A
V
Pin name
CC
0
SS
: option) only
Type name
CMOS Input level
CMOS Input level
M5M44260Cxx-5,-5S
M5M44260Cxx-6,-6S
M5M44260Cxx-7,-7S
Self refresh current
Extended refresh current
~A
1
~DQ
8
16
Lower byte control
Address inputs
Data inputs / outputs
Row address strobe input
column address strobe input
Upper byte control
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
column address strobe input
(max.ns)
access
RAS
time
70
50
60
Function
(max.ns)
access
CAS
time
13
15
20
0
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Address
(max.ns)
0
~A
access
~A
time
25
30
35
8
8
)
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
) *
(max.ns)
access
time
13
15
20
OE
(min.ns)
550µW (Max) *
Cycle
110
130
688mW (Max)
605mW (Max)
523mW (Max)
time
5.5mW (Max)
150µA (Max)
150µA (Max)
90
M5M44260CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
A
A
A
A
W
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
25
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
23
MITSUBISHI LSIs
NC: NO CONNECTION
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
V
A
A
A
A
A
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
SS
SS
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

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