AGL1000V2-FGG144I Actel, AGL1000V2-FGG144I Datasheet

AGL1000V2-FGG144I

Manufacturer Part Number

AGL1000V2-FGG144I

Description

Manufacturer

Actel

Datasheets

1.AGL1000V2-FGG144I.pdf (212 pages)

2.AGL1000V2-FGG144I.pdf (212 pages)

Specifications of AGL1000V2-FGG144I

Lead_time

Pack_quantity

160

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

AGL1000V2-FGG144I

Manufacturer:

Microsemi SoC

Quantity:

10 000

Current page: 1 of 212
Download datasheet (7Mb)

December 2008

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

High Capacity

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

IGLOO Product Family

IGLOO Devices

ARM-Enabled IGLOO Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

2. AGL060 in CS121 does not support the PLL.

3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

4. The M1AGL250 device does not support this package.

5. Device/package support TBD

6. For higher densities and support of additional features, refer to the

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

• Segmented, Hierarchical Routing and Clock Structure

UC/CS

QFN

VQFP

FBGA

1 AGL015 and AGL030 devices do not support this feature.

Technology

Consumption while Maintaining FPGA Content

Mode

Standard (AES) Decryption (except ARM

devices) via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

handbook.

Technology

Enables

AGL015

QN68

15 k

128

384

1 k

–

Ultra-Low

-enabled IGLOO

QN48, QN68,

UC81/CS81

AGL030

QN132

VQ100

30 k

256

768

1 k

–

Power

AGL060

FG144

QN132

VQ100

CS121

1,536

60 k

512

Yes

1 k

Advanced I/O

Clock Conditioning Circuit (CCC) and PLL

Embedded Memory

ARM Processor Support in IGLOO FPGAs

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

• Six CCC Blocks, One with an Integrated PLL

• Configurable

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

• True Dual-Port SRAM (except ×18)

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

AGL125

QN132

VQ100

FG144

CS196

‡ Supported only by AGL015 and AGL030 devices.

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

LVCMOS 2.5 V / 5.0 V Input

LVDS (AGL250 and above)

Capabilities, and External Feedback

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

with or without Debug

3,072

125 k

1,024

133

Yes

1 k

IGLOOe Low-Power Flash FPGAs with Flash*Freeze

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

QN132

AGL250

CS196

VQ100

FG144

250 k

2,048

6,144

143

Yes

1 k

4,5

Phase

I/O

AGL400

FG144,

FG256,

CS196

FG484

400 k

9,216

194

Yes

1 k

Standards:

Shift,

–

and Drive Strength

Multiply/Divide,

AGL600

FG144,

FG256,

13,824

FG484

CS281

600 k

‡

108

235

Yes

1 k

–

LVTTL,

AGL1000

FG144,

FG256,

24,576

FG484

CS281

1 M

144

300

Yes

1 k

LVCMOS

–

1 RAM

v1.3

Delay

, and

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