APA075-FGG144I Actel, APA075-FGG144I Datasheet
APA075-FGG144I
Manufacturer Part Number
APA075-FGG144I
Description
BGA 144/IC,FPGA,3072-CELL,CMOS
Manufacturer
Actel
Datasheet
1.APA075-FG144I.pdf
(68 pages)
Specifications of APA075-FGG144I
Lead_time
42
Pack_quantity
160
Comm_code
85423990
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
APA075-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC
Features and Benefits
High Capacity
•
•
•
Reprogrammable Flash Technology
•
•
•
•
Performance
•
•
•
Secure Programming
•
Low Power
•
•
•
High Performance Routing Hierarchy
•
•
Table 1 • ProASIC
December 2003
© 2003 Actel Corporation
Device
Maximum System Gates
Maximum Tiles (Registers)
Embedded RAM Bits (k=1,024
bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
75,000 to 1 million System Gates
27k to 198kbits of Two-Port SRAM
66 to 712 User I/Os
0.22
Live at Power-Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Power-Up Cycles
3.3V, 32-bit PCI (up to 50 MHz)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
Prevents Read Back of Programming Bitstream
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
Ultra-Fast Local and Long-Line Network
High Speed Very Long-Line Network
LM Flash-based CMOS Process
PLUS
PLUS
Product Profile
Flash Family FPGAs
APA075
100, 144
75,000
3,072
27k
158
208
144
Yes
Yes
12
24
2
2
4
–
APA150
144, 256
150,000
6,144
242
100
36k
208
456
Yes
Yes
16
32
2
2
4
)
APA300
144, 256
300,000
8,192
72k
290
208
456
Yes
Yes
32
32
•
•
I/O
•
•
•
•
•
•
Unique Clock Conditioning Circuitry
•
•
•
Standard FPGA and ASIC Design Flow
•
•
ISP Support
•
SRAMs and FIFOs
•
•
2
2
4
–
High Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
Schmitt-Trigger Option on Every Input
2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across ProASIC
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Frontend Tools
Efficient Design through Frontend Timing and Gate Optimization
In-System Programming (ISP) via JTAG Port
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
144, 256, 484 256, 484, 676
APA450
450,000
12,288
108k
344
208
456
Yes
Yes
48
48
2
2
4
–
APA600
600,000
21,504
126k
454
208
456
Yes
Yes
56
56
2
2
4
–
APA750
676, 896
750,000
32,768
144k
562
208
456
Yes
Yes
64
64
2
2
4
PLUS
–
Family
APA1000
1,000,000
896, 1152
56,320
198k
712
208
456
Yes
Yes
88
88
v3 .4
2
2
4
–
TM
i
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