M1A3P400-FGG144

Manufacturer Part NumberM1A3P400-FGG144
Description
ManufacturerActel
M1A3P400-FGG144 datasheet
 


Specifications of M1A3P400-FGG144

Lead_time555Pack_quantity160
Comm_code85423990  
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ProASIC3 Flash Family FPGAs
with Optional Soft ARM
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC
devices) via JTAG (IEEE 1532–compliant)
®
• FlashLock
to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
ProASIC3 Product Family
ProASIC3 Devices
A3P015
1
ARM7 Devices
1
Cortex-M1 Devices
System Gates
15 k
Typical Equivalent Macrocells
128
VersaTiles (D-flip-flops)
384
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
1 k
2
Secure (AES) ISP
Integrated PLL in CCCs
3
VersaNet Globals
6
I/O Banks
2
Maximum User I/Os
49
Package Pins
QFN
QN68
VQFP
TQFP
PQFP
FBGA
Notes:
1. Refer to the
CoreMP7
datasheet or
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
5. The M1A3P250 device does not support this package.
† A3P015 and A3P030 devices do not support this feature.
February 2008
© 2008 Actel Corporation
®
Support
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable
®
Capabilities and External Feedback
3
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
A3P030
A3P060
A3P125
A3P250
M1A3P250
30 k
60 k
125 k
256
512
1,024
768
1,536
3,072
18
36
4
8
1 k
1 k
1 k
Yes
Yes
1
1
6
18
18
2
2
2
81
96
133
QN132
QN132
QN132
QN132
VQ100
VQ100
VQ100
VQ100
TQ144
TQ144
PQ208
PQ208
FG144
FG144
FG144/256
Cortex-M1
product brief for more information.
ProASIC3E Flash Family FPGAs
‡ Supported only by A3P015 and A3P030 devices.
I/O
Standards:
LVTTL,
LVCMOS
and Drive Strength
Phase-Shift,
Multiply/Divide,
A3P400
A3P600
M1A3P400
M1A3P600
250 k
400 k
600 k
6,144
9,216
13,824
36
54
108
8
12
24
1 k
1 k
1 k
Yes
Yes
Yes
1
1
1
18
18
18
4
4
4
157
194
235
5
PQ208
PQ208
5
FG144/256/
FG144/256/
484
484
handbook.
v1.0
®
3.3 V /
and LVCMOS
Delay
A3P1000
M7A3P1000
M1A3P1000
1 M
24,576
144
32
1 k
Yes
1
18
4
300
PQ208
FG144/256/
484
I