NT5DS16M16CS-5T Nanya Technology, NT5DS16M16CS-5T Datasheet

NT5DS16M16CS-5T

Manufacturer Part Number

NT5DS16M16CS-5T

Description

Manufacturer

Nanya Technology

Datasheet

1.NT5DS16M16CS-5T.pdf (77 pages)

Specifications of NT5DS16M16CS-5T

Date_code

10+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

NT5DS16M16CS-5T

Manufacturer:

Quantity:

291

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA

Quantity:

213

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA

Quantity:

2 526

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA

Quantity:

118

Company:

BOSTOCK HK LIMITED

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA

Quantity:

8 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

NT5DS16M16CS-5T

Manufacturer:

NANYA/南亚

Quantity:

20 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

NT5DS16M16CS-5TI

Manufacturer:

NANYA/南亚

Quantity:

20 000

Current page: 1 of 77
Download datasheet (3Mb)

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT

NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS

256Mb DDR SDRAM

Features

CAS Latency and Frequency

Description

NT5DS64M4CT, NT5DS32M8CT and NT5DS16M16CT,

NT5DS64M4CS, NT5DS32M8CS and NT5DS16M16CS are

die C of 256Mb SDRAM devices based using DDR interface.

They are all based on Nanya’s 110 nm design process.

The 256Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads

and by the memory controller during Writes. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 256Mb DDR SDRAM operates from a differential clock

(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive

edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-

ented; accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be

accessed. The address bits registered coincident with the

REV 0.5

Sept 15, 2004

• DDR 256M bit, die C, based on 110nm design rules

• Double data rate architecture: two data transfers per

• Bidirectional data strobe (DQS) is transmitted and

• DQS is edge-aligned with data for reads and is center-

Latency

CAS

2.5

clock cycle

received with data, to be used in capturing data at the

receiver

aligned with data for writes

Maximum Operating Frequency

DDR400

(5T)

166

200

(MHz)

DDR333

(6K)

133

166

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4, or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-

ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving

Power Down mode. All inputs are compatible with the JEDEC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and

• Burst lengths: 2, 4, or 8

• CAS Latency: 2/2.5(DDR333) , 2.5/3(DDR400)

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8 s Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

• V

• Available in Halogen and Lead Free packaging

data mask referenced to both edges of DQS

= V

DDQ

= 2.5V

= 2.6V

NANYA TECHNOLOGY CORP

0.2V (DDR333)

0.1V (DDR400)

Related parts for NT5DS16M16CS-5T

Related keywords

NT5DS16M16CS-5T datasheet
NT5DS16M16CS-5T data sheet
NT5DS16M16CS-5T pdf datasheet
NT5DS16M16CS-5T component
NT5DS16M16CS-5T part
NT5DS16M16CS-5T distributor
NT5DS16M16CS-5T RoHS
NT5DS16M16CS-5T datasheet download