AS4C256K16E0-30 ALSC [Alliance Semiconductor Corporation], AS4C256K16E0-30 Datasheet - Page 7

• Manufacturer Part Number: AS4C256K16E0-30
• Description: 5V 256Kx16 CMOS DRAM (EDO)
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

Notes
1
2
3
4
5
6
7
8
9
10 t
11 t
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
14 t
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Read cycle waveform
4/11/01; v.1.1
Address
I
I
An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume t
V
Operation within the t
specified t
Operation within the t
specified t
Assumes three state test load (5 pF and a 380
Either t
(min) and t
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
CC1
CC1
OFF
WCS
ASC
IH
UCAS,
LCAS
V
t
RWD
RAS
CC
, I
(min) and V
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
, t
WE
and I
OE
I/O
CC3
.
WCH
t
RCH
CP
(min), t
, I
CC4
RCD
RAD
to achieve t
, t
Undefined/don’t care
or t
CC4
WH
RWD
depend on output loading. Specified values are obtained with the output open.
(max) limit, then access time is controlled exclusively by t
(max) limit, then access time is controlled exclusively by t
, and I
RRH
CWD
IL
, t
t
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
CWD
WH
must be satisfied for a read cycle.
CC6
PC
RCD
RAD
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
t
and t
CWD
(min) and t
depend on cycle rate.
(max) limit insures that t
(max) limit insures that t
T
t
CRP
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V
AWD
(min) and t
t
Row Address
ASR
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
CAP
(max) values.
AWD
t
RAH
CAA
t
t
Thevenin equivalent).
RAD
AWD
or t
RAC
RAC
CAC
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
t
Alliance Semiconductor
RCD
(max) can be met. t
(max) can be met. t
or t
t
t
CAP
AR
RAC
.
t
RCS
t
RAS
t
CSH
t
ASC
Col Address
t
CLZ
CAC
AA
t
Rising input
.
RAL
RCD
.
RAD
t
AA
t
t
RC
CAH
®
(max) is specified as a reference point only. If t
(max) is specified as a reference point only. If t
t
t
CAC
RSH
t
t
OEA
CAS
t
ROH
Data Out
t
RRH
t
OEZ
t
RP
t
OFF
IL
t
RCH
(min)
Falling input
IH
AS4C256K16E0
RCD
RAD
and V
is greater than the
is greater than the
GND and V
IL
.
7 of 24
WS
IH
(max)
RWD
t
WS