HT48CA0-3 HOLTEK [Holtek Semiconductor Inc], HT48CA0-3 Datasheet
HT48CA0-3
Related parts for HT48CA0-3
HT48CA0-3 Summary of contents
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... RAM General Description The HT48RA0-3/HT48CA0-3 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48CA0-3 is fully pin and functionally compatible with the OTP version HT48RA0-3 device. Rev.1.10 HT48RA0-3/HT48CA0-3 ...
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... Block Diagram Pin Assignment Rev.1.10 HT48RA0-3/HT48CA0-3 2 October 12, 2007 ...
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... REM Output Source Current OH R Pull-high Resistance PH V Start Voltage to ensure DD V POR Power-on Reset V Rise Rate to ensure DD R POR Power-on Reset Rev.1.10 HT48RA0-3/HT48CA0-3 Description +4.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions Min. V Conditions DD 2.0 No load, f ...
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... SYS SYS Functional Description Execution Flow The HT48RA0-3/HT48CA0-3 system clock type clock which requires the connection of an external resistor for its operation internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle ...
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... Note: *9~*0: Table location bits P9~P8: Current program counter bits Rev.1.10 HT48RA0-3/HT48CA0-3 ble is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remain- ing 2 bits are read The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP read/write register (07H), where P indicates the table location ...
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... TO set by a WDT time-out. 6~7 Unused bit, read as 0 Rev.1.10 HT48RA0-3/HT48CA0-3 Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation to [00H] accesses the data memory pointed (01H). Reading location 00H itself indirectly will return the result 00H ...
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... DD Temperature = + 4MHz SYS Rev.1.10 HT48RA0-3/HT48CA0-3 Watchdog Timer - WDT The WDT clock source is implemented by the instruction clock which is the system clock divided by 4. The clock source is processed by a frequency divider and a prescaler to provide various time out periods. Clock Source WDT time out period = Where n= 8~11 selected by a configuration option ...
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... Low Voltage reset WDT time-out reset during normal operation Reset Timing Chart Rev.1.10 HT48RA0-3/HT48CA0-3 Some registers remain unchanged during reset condi- tions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets ...
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... Input/Output Ports There are an 8-bit bidirectional input/output port, a 6-bit input with 2-bit I/O port in the HT48RA0-3/HT48CA0-3, labeled PA and PB which are mapped to [12H], [14H] of the Data Memory, respectively. Each bit of PA can be se- lected as NMOS output or Schmitt trigger input with pull-high resistor by a software instruction ...
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... Timer operation end flag, initial 7 TOEF value TSR1 (19H) Register Rev.1.10 HT48RA0-3/HT48CA0-3 PA, PB0~PB1 Input/Output Lines PB2~PB6 Input Lines PB7 Input Line Timer Operation The timer starts counting down when a value other than 0 is set for the down counter with a timer manipulation instruction ...
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... Timer output time = (Set value+1) 64/f An example is shown below. MOV A,0FFH MOV TSR0,A MOV A,01H MOV TSR1,A SET TSR1.1 Rev.1.10 HT48RA0-3/HT48CA0-3 In the case above, the timer output time is as follows. (Set value+1) 64/f = (511+ 8.192ms By setting the flag (t9) that enables the timer output to =64/f ...
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... The carrier is started by clearing CARY(CARH1.1)= 0 Configuration of Remote Controller Carrier Generator Note: 1. Bit 9 of the modulo register for setting the low-level period (CARL) is fixed t9: Flag that enables timer output (timer block, see Timer Configuration) Rev.1.10 HT48RA0-3/HT48CA0-3 Bit5 Bit4 Bit3 Bit2 CL. ...
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... Timer Output when Carrier Is an Output Note: When the carrier signal is active and during the time when the signal is high, if the timer output should go low, the carrier signal will first complete its high level period before going low. Rev.1.10 HT48RA0-3/HT48CA0 SYS ...
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... Carrier Frequency Setting (f Rev.1.10 HT48RA0-3/HT48CA0-3 9-bit Down Counter (TSR0.0~TSR0.7, TSR1.0) 0 Low-level output Other than 0 0 64/fsys (with carrier output) Other than 0 Carrier output (Note) Low-level output High-level output f ...
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... Since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters the reset mode. Configuration Options The following table shows eight kinds of configuration options for the HT48RA0-3/HT48CA0-3. All the configuration op- tions must be defined to ensure proper system functioning. No. ...
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... Application Circuits Example Rev.1.10 HT48RA0-3/HT48CA0-3 16 October 12, 2007 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev.1.10 HT48RA0-3/HT48CA0-3 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev.1.10 HT48RA0-3/HT48CA0-3 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev.1.10 HT48RA0-3/HT48CA0-3 Description 19 Cycles Flag Affected ...
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... ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev.1.10 HT48RA0-3/HT48CA0-3 20 October 12, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev.1.10 HT48RA0-3/HT48CA0-3 addr 21 October 12, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev.1.10 HT48RA0-3/HT48CA0 October 12, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev.1.10 HT48RA0-3/HT48CA0-3 addr 23 October 12, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev.1.10 HT48RA0-3/HT48CA0-3 Stack Stack Stack [m]. 0~6) 24 October 12, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev.1.10 HT48RA0-3/HT48CA0-3 [m]. 0~6) 25 October 12, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev.1.10 HT48RA0-3/HT48CA0-3 [ October 12, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev.1.10 HT48RA0-3/HT48CA0-3 0 [m] [ October 12, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev.1.10 HT48RA0-3/HT48CA0-3 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 28 October 12, 2007 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev.1.10 HT48RA0-3/HT48CA0-3 29 October 12, 2007 ...
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... Package Information 20-pin SOP (300mil) Outline Dimensions Symbol Rev.1.10 HT48RA0-3/HT48CA0-3 Dimensions in mil Min. Nom. 394 290 14 490 Max. 419 300 20 510 104 October 12, 2007 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev.1.10 HT48RA0-3/HT48CA0-3 Dimensions in mil Min. Nom. 228 150 8 335 Max. 244 158 12 347 October 12, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev.1.10 HT48RA0-3/HT48CA0-3 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 16.8+0.3 0.2 22.2 0.2 32 October 12, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev.1.10 HT48RA0-3/HT48CA0-3 Dimensions in mm 24.0+0.3 0.1 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 Dimensions in mm 16.0+0.3 0.1 8.0 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 6 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev.1.10 HT48RA0-3/HT48CA0-3 34 October 12, 2007 ...