HT48R10A-1_09 HOLTEK [Holtek Semiconductor Inc], HT48R10A-1_09 Datasheet
HT48R10A-1_09
Related parts for HT48R10A-1_09
HT48R10A-1_09 Summary of contents
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... Watchdog Timer 1024 14 program memory ROM General Description The HT48R10A-1/HT48C10-1 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48C10-1 is fully pin and functionally compatible with the OTP version HT48R10A-1 device ...
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... Block Diagram Pin Assignment Rev. 2.01 HT48R10A-1/HT48C10-1 2 January 9, 2009 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 2.01 HT48R10A-1/HT48C10-1 Description +6.0V Storage Temperature ............................ 125 ...
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... V Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset LVR I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH Rev. 2.01 HT48R10A-1/HT48C10-1 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V No load, f =4MHz SYS 5V 3V ...
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... Watchdog Time-out Period t WDT2 (System Clock) Watchdog Time-out Period t WDT3 (RTC OSC) t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 2.01 HT48R10A-1/HT48C10-1 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 400 3.3V~5.5V 400 3.2MHz 1800 1.6MHz 900 ...
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... Return from Subroutine S9 Note: *9~*0: Program counter bits #9~#0: Instruction code bits Rev. 2.01 HT48R10A-1/HT48C10-1 When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. ...
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... Note: *9~*0: Table location bits @7~@0: Table pointer bits Rev. 2.01 HT48R10A-1/HT48C10-1 ferred to the lower portion of TBLH, and the remaining 2 bits are read The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP read/write register (07H), which indicates the table location ...
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... PBC;15H, PCC;17H). The remain- ing space before the 40H is reserved for future ex- RAM Mapping Rev. 2.01 HT48R10A-1/HT48C10-1 panded usage and reading these locations will get 00H . The general purpose data memory, addressed from 40H to 7FH, is used for data and control informa- tion under instruction commands ...
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... Unused bit, read Unused bit, read as 0 Rev. 2.01 HT48R10A-1/HT48C10-1 (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupts are triggered by a high to low transi- tion of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set ...
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... No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Rev. 2.01 HT48R10A-1/HT48C10-1 Function INTC (0BH) Register oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 24k to 1M ...
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... CLR WDT times selection option . If the CLR WDT is selected (i.e. CLRWDT times equal Rev. 2.01 HT48R10A-1/HT48C10-1 Watchdog Timer one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT ...
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... SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Rev. 2.01 HT48R10A-1/HT48C10-1 Reset Timing Chart Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference ...
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... Unused bit, read define the operating mode 01=Event count mode (external clock) 6 TM0 10=Timer mode (internal clock) 7 TM1 11=Pulse width measurement mode 00=Unused Rev. 2.01 HT48R10A-1/HT48C10-1 RES Reset RES Reset (Normal Operation) (HALT) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 000H -uuu uuuu ...
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... TMRC) should be set the pulse width measurement mode, the TON will be cleared au- tomatically after the measurement cycle is completed. Rev. 2.01 HT48R10A-1/HT48C10-1 Timer/Event Counter But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources ...
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... B buzzer option BZ, x don't care C CMOS output Rev. 2.01 HT48R10A-1/HT48C10-1 mented; on reading them returned whereas writing then results in a no-operation. See Application note. There is a pull-high option available for all I/O ports (byte option). Once the pull-high option of an I/O port is se- lected, all I/O lines have pull-high resistors ...
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... Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the reset mode. Rev. 2.01 HT48R10A-1/HT48C10-1 The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between V ...
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... PA CMOS or Schmitt input 6 PA, PB, PC pull-high enable or disable (By port) 7 BZ/BZ enable or disable 8 LVR enable or disable System oscillator 9 Ext.RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4 10 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Rev. 2.01 HT48R10A-1/HT48C10-1 Options /4 or RTC oscillator or disable SYS or RTCOSC SYS 17 January 9, 2009 ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 2.01 HT48R10A-1/HT48C10-1 C1, C2 0pF 10pF ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 2.01 HT48R10A-1/HT48C10-1 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 2.01 HT48R10A-1/HT48C10-1 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 2.01 HT48R10A-1/HT48C10-1 Description 21 Cycles Flag Affected ...
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... ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 2.01 HT48R10A-1/HT48C10-1 22 January 9, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 2.01 HT48R10A-1/HT48C10-1 addr 23 January 9, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 2.01 HT48R10A-1/HT48C10 January 9, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 2.01 HT48R10A-1/HT48C10-1 addr 25 January 9, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 2.01 HT48R10A-1/HT48C10-1 Stack Stack Stack [m]. 0~6) 26 January 9, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 2.01 HT48R10A-1/HT48C10-1 [m]. 0~6) 27 January 9, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 2.01 HT48R10A-1/HT48C10-1 [ January 9, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 2.01 HT48R10A-1/HT48C10-1 0 [m] [ January 9, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 2.01 HT48R10A-1/HT48C10-1 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 30 January 9, 2009 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 2.01 HT48R10A-1/HT48C10-1 31 January 9, 2009 ...
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... MS-001d (see fig1) Symbol MS-001d (see fig2) Symbol Rev. 2.01 HT48R10A-1/HT48C10-1 Fig2. 1/2 Lead Packages Dimensions in mil Min. Nom. 1230 240 115 115 14 45 100 300 Dimensions in mil Min. Nom. 1160 240 115 115 14 45 100 ...
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... MO-095a (see fig2) Symbol Rev. 2.01 HT48R10A-1/HT48C10-1 Dimensions in mil Min. Nom. 1145 275 120 110 14 45 100 300 33 Max. 1185 295 150 150 22 60 325 430 January 9, 2009 ...
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... SOP (300mil) Outline Dimensions MS-013 Symbol Rev. 2.01 HT48R10A-1/HT48C10-1 Dimensions in mil Min. Nom. 393 256 12 598 Max. 419 300 20 613 104 January 9, 2009 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.01 HT48R10A-1/HT48C10-1 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 24.8 30.2 0.2 35 January 9, 2009 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.01 HT48R10A-1/HT48C10-1 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 36 January 9, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.01 HT48R10A-1/HT48C10-1 37 January 9, 2009 ...