SII141 ETC1 [List of Unclassifed Manufacturers], SII141 Datasheet - Page 8

• Manufacturer Part Number: SII141
• Description: SiI 141B PanelLink Digital Receiver
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Differential Signal Data Pin Description
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
EXT_RES
Reserved Pin Description
Power and Ground Pin Description
Application Information
The SiI141B is pin for pin compatible with the SiI141 but includes two new features, HSYNC de-jitter and power
down when the clock is inactive.
HSYNC de-jitter enables the 141B to operate properly even when the HSYNC signal contains jitter. Pin 75 is used
to enable or disable this capability (a reserved pin tied high on the SiI141). Tying this pin low enables the HSYNC
de-jitter circuitry while tying it high disables the circuitry. The HSYNC de-jitter circuitry operates normally with most
VESA standard timings. Some DOS mode resolutions do not have timings that are a multiple of eight (HSYNC
and VSYNC total times and front and back porch times are multiples of eight pixel times). If they are not a multiple
of eight, operation is not guaranteed and the HSYNC de-jitter circuitry should be turned off. When HSYNC de-
jitter is enabled, the circuitry will introduce anywhere from 0 to 7 CLK delays in the HSYNC signal relative to the
output data.
The SiI141B includes a new power saving feature, power down with clock detect circuit. The SiI141B will go into a
low power mode when there is no video clock coming from the transmitter. In this mode the entire chip is powered
down except the clock detect circuitry. During this mode digital I/O are set to a high impedance (tri-state) mode. A
weak internal pull-down device brings each output to ground. The device power down and wake-up times are
shown in Figures 6 and 7.
The SiI141B also includes a sync detect feature for pin compatibility with SiI141. In both the SiI141 and SiI141B,
SCDT goes low when DE is inactive.
Silicon Image, Inc.
Pin Name
Pin Name
Pin Name
OVCC
OGND
AGND
PGND
RSVD
AVCC
PVCC
VCC
GND
Pin #
Pin #
Pin #
39
50
61
11
37
62
15
28
48
13
26
46
63
69
66
72
77
78
70
71
67
68
64
65
74
73
76
1
4
Analog
Analog
Analog
Ground Digital GND.
Ground Output GND.
Ground Analog GND.
Ground PLL GND.
Type
Power
Power
Power
Power
Type
Type
Out
Description
TMDS Low Voltage Differential Signal input data pairs.
TMDS Low Voltage Differential Signal input clock pair.
Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable.
In the common case of 50
and this pin.
Description
This signal must be left unconnected.
Description
Core VCC, must be set to 3.3V.
Output VCC, must be set to 3.3V.
Analog VCC, must be set to 3.3V.
PLL VCC, must be set to 3.3V.
transmission line, an external 530
SiI 141B
8
resistor must be connected between AVCC
Subject to Change without Notice
SiI-DS-0037-C