HT49CA0 HOLTEK [Holtek Semiconductor Inc], HT49CA0 Datasheet
HT49CA0
Related parts for HT49CA0
HT49CA0 Summary of contents
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... LCD remote controllers and various subsystem controllers. The HT49CA0 is under development and will be avail- able soon. 1 with LCD October 24, 2007 ...
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... Block Diagram Pin Assignment Rev. 1.20 HT49RA0/HT49CA0 2 October 24, 2007 ...
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... Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions Min. V Conditions DD 2.0 No load, f =4MHz 3V SYS No load, system HALT, 3V LCD off at HALT No load, system HALT, 3V LCD On at HALT, C type 3 HT49RA0/HT49CA0 V . LCD DD Ta=25 C Typ. Max. Unit 3.6 V 0.7 1 October 24, 2007 ...
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... External Reset Low Pulse Width RES t Low Voltage Width to Reset LVR t System Start-up Timer Period SST t Interrupt Pulse Width INT Note: *t =1/f SYS SYS Rev. 1.20 HT49RA0/HT49CA0 Test Conditions Min. V Conditions DD No load, system HALT 3V LCD On at HALT, C type ...
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... S10 Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 1.20 HT49RA0/HT49CA0 After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ...
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... These areas may function as a normal ROM depending upon the user s requirements. Program Memory Table Location * Table Location P10~P8: Current program Counter bits 6 HT49RA0/HT49CA0 * October 24, 2007 ...
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... RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Rev. 1.20 HT49RA0/HT49CA0 RAM Mapping Accumulator - ACC The accumulator (ACC) is related to the ALU opera- tions also mapped to location 05H of the RAM and is capable of operating with immediate data ...
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... WDT time-out Unused bit, read as 0 Rev. 1.20 HT49RA0/HT49CA0 Once an interrupt subroutine is serviced, other inter- rupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded ...
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... Real time clock request flag (1=active; 0=inactive Unused bit, read as 0 Rev. 1.20 HT49RA0/HT49CA0 Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply ...
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... LCDEN, RTCEN=1, 0 LCD off, RTC off LCD on, RTC off LCD off, RTC off LCD on, RTC off LCD off, RTC on LCD on, RTC on LCD off, RTC on LCD on, RTC on 10 HT49RA0/HT49CA0 LCDEN, RTCEN=1, 1 LCD on, RTC off LCD on, RTC off LCD on, RTC on LCD on, RTC on October 24, 2007 ...
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... Timer/Event Counter for getting a longer time-out period. RT2 RT1 Note: * not recommended to be used Watchdog Timer 11 HT49RA0/HT49CA0 Time Base RT0 RTC Clock Divided Factor 10 11 ...
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... The functional unit chip reset status is shown below. Program Counter Interrupt (system SYS Prescaler, Divider WDT, RTC, Time base Timer/Event Counter Off Input/output ports Stack Pointer 12 HT49RA0/HT49CA0 RESET Conditions 000H Disabled Cleared Cleared. After master reset, WDT starts counting Input mode Points to the top of the stack October 24, 2007 ...
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... HT49RA0/HT49CA0 RES Reset WDT Time-out (HALT) (HALT)* -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu ...
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... TM1 11=Pulse Width measurement mode (External clock) 00=Unused Rev. 1.20 HT49RA0/HT49CA0 mode can be used to count the high or low level duration of the external signal (TMR), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event coun- ter starts counting at the current contents in the timer/event counter and ends at FFH ...
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... Rev. 1.20 HT49RA0/HT49CA0 Carrier Generator The HT49RA0/HT49CA0 provides a carrier output which shares the pin with PC0. It can be selected carrier output (REM) or level output pin (PC0) by code option. If the carrier output option is selected, setting PC0 enable carrier output and setting PC0 disable it at low level output ...
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... Input/Output Ports There are an 8-bit bidirectional input/output port, a 8-bit in- put port and one-bit input/output port in the HT49RA0/HT49CA0, labeled as PA, PB and PC which are mapped to [12H], [14H], [16H] of the RAM respec- tively. Each bit of PA can be selected as NMOS output or Schmitt trigger with pull-high resistor by software instruc- tion ...
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... The figure illus- trates the mapping between the display memory and LCD pattern for the devices. Display Memory Rev. 1.20 HT49RA0/HT49CA0 PC Input/Output Ports LCD Driver Output The output number of the LCD driver device can option. The bias type LCD driver can be C type only ...
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... LCD Driver Output (1/3 Duty, 1/2 Bias, C Type) Rev. 1.20 HT49RA0/HT49CA0 18 October 24, 2007 ...
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... LCD Driver Output (1/4 Duty, 1/3 Bias, C Type) Rev. 1.20 HT49RA0/HT49CA0 19 October 24, 2007 ...
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... LVDC Enable Enable On Enable Enable Off Enable Disable On Enable Disable Off Disable Enable X Disable Disable X Rev. 1.20 HT49RA0/HT49CA0 Function RTCC (09H) Register VREF Generator LVR Comparator Enable Enable Enable Enable Enable Disable Disable Disable Enable Enable Disable Disable 20 LVD Comparator Enable Disable ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2 Low voltage state has to be maintained for over 1ms, then after a 1ms delay the device enters the reset mode. Rev. 1.20 HT49RA0/HT49CA0 The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock ...
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... SYS 23 Carrier frequency: f /24, f SYS SYS Rev. 1.20 Options SYS SYS SYS /32, f /64 for 1/2 duty cycle SYS SYS /48, f /96 for 1/2 duty or 1/3 duty cycle SYS 22 HT49RA0/HT49CA0 October 24, 2007 ...
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... RES pin is kept as short as possible, to avoid noise interference. 2. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.20 HT49RA0/HT49CA0 23 W October 24, 2007 ...
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... Example Rev. 1.20 HT49RA0/HT49CA0 October 24, 2007 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.20 HT49RA0/HT49CA0 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.20 HT49RA0/HT49CA0 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 HT49RA0/HT49CA0 Description 27 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.20 HT49RA0/HT49CA0 28 October 24, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.20 HT49RA0/HT49CA0 addr 29 October 24, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT49RA0/HT49CA0 October 24, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.20 HT49RA0/HT49CA0 addr 31 October 24, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.20 Stack Stack Stack [m]. 0~6) 32 HT49RA0/HT49CA0 October 24, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.20 [m]. 0~6) 33 HT49RA0/HT49CA0 October 24, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.20 [ HT49RA0/HT49CA0 October 24, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.20 0 [m] [ HT49RA0/HT49CA0 October 24, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.20 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 36 HT49RA0/HT49CA0 October 24, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.20 HT49RA0/HT49CA0 37 October 24, 2007 ...
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... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Rev. 1.20 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT49RA0/HT49CA0 Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 October 24, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT49RA0/HT49CA0 39 October 24, 2007 ...