DAC0854CMJ/883 NSC [National Semiconductor], DAC0854CMJ/883 Datasheet - Page 11

• Manufacturer Part Number: DAC0854CMJ/883
• Description: 8-Bit Voltage-Output
• Manufacturer: NSC [National Semiconductor]

Bit
Digital Interface
Table III lists the instruction set for the READ mode By the
appropriate setting of the global (G) and address (A1 and
A0) bits one can select a specific DAC to be read or one
can read all the DACs in succession starting with DAC 1
The R F bit determines whether the data changes on the
rising or the falling edge of the system clock With the R F
bit high the data changes on the rising edge that occurs 1
clock cycles after the end of the instruction byte With the
R F bit low the data changes on the falling edge that oc-
Power Fail Function
If a power failure occurs on the system using the DAC0854
then the INT pin will be pulled low on the next power-up
cycle To force this output high again and reset this flag the
CS pin will have to be brought low When this is done the
INT output will be pulled high again via an external 10 k
pull-up resistor This feature may be used by the microproc-
essor to discard data whose integrity is in question
SB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RD WR
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
Bit
G
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
3
(Continued)
Bit
R F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
4
Bit
M L
TABLE III READ MODE Instruction Set
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
5
Bit
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
6
Bit
A0
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
7
curs 1 clock cycle after the end of the instruction byte One
can choose to read the data back MSB first or LSB first by
setting the M L bit (See Figures 3 and 4 )
An asynchronous update of all the DAC outputs can be
achieved by taking AU low The contents of the input regis-
ters are loaded into the DAC registers with the update oc-
curring on the falling edge of AU CS must be held high
during an asynchronous update
All DAC registers will have their contents reset to all zeros
on power up
Power Supplies
The DAC0854 is designed to operate from a
supply There are two supply pins AV
pins allow separate external bypass capacitors for the ana-
log and digital portions of the circuit To guarantee accurate
conversions the two supply pins should each be bypassed
with a 0 1
tantalum capacitor
Read DAC 1 LSB first data changes on the falling edge
Read DAC 2 LSB first data changes on the falling edge
Read DAC 3 LSB first data changes on the falling edge
Read DAC 4 LSB first data changes on the falling edge
Read DAC 1 MSB first data changes on the falling edge
Read DAC 2 MSB first data changes on the falling edge
Read DAC 3 MSB first data changes on the falling edge
Read DAC 4 MSB first data changes on the falling edge
Read DAC 1 LSB first data changes on the rising edge
Read DAC 2 LSB first data changes on the rising edge
Read DAC 3 LSB first data changes on the rising edge
Read DAC 4 LSB first data changes on the rising edge
Read DAC 1 MSB first data changes on the rising edge
Read DAC 2 MSB first data changes on the rising edge
Read DAC 3 MSB first data changes on the rising edge
Read DAC 4 MSB first data changes on the rising edge
Read all DACs LSB first data changes on the falling edge
Read all DACs MSB first data changes on the falling edge
Read all DACs LSB first data changes on the rising edge
Read all DACs MSB first data changes on the rising edge
F ceramic capacitor in parallel with a 10
Description
CC
and DV
a
5V (nominal)
CC
These
F