ADS-CCD1201 CANDD [C&D Technologies], ADS-CCD1201 Datasheet

ADS-CCD1201

Manufacturer Part Number

ADS-CCD1201

Description

12-Bit, 1.2MHz, Sampling A/D Optimized for CCD Appl

Manufacturer

CANDD [C&D Technologies]

Datasheet

1.ADS-CCD1201.pdf (8 pages)

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DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.)

FEATURES

GENERAL DESCRIPTION

The functionally complete, easy-to-use ADS-CCD1201 is a

12-bit, 1.2MHz Sampling A/D Converter whose performance

and production testing have been optimized for use in

electronic imaging applications, particularly those employing

charge coupled devices (CCD’s) as their photodetectors. The

ADS-CCD1201 delivers the lowest noise (400µVrms) and the

best differential nonlinearity error (±0.35LSB max.) of any

commercially available 12-bit A/D in its speed class. It can

respond to full scale input steps (from empty to full well) with

less than a single count of error, and its input is immune to

overvoltages that may occur due to blooming.

Packaged in an industry-standard, 24-pin, ceramic DDIP, the

ADS-CCD1201 requires ±15V (or ±12V) and +5V supplies and

typically consumes 1.7 (1.4) Watts. The device is 100%

production tested for all critical performance parameters and is

fully specified over both the 0 to +70°C and –55 to +125°C

operating temperature ranges.

For those applications using correlated double sampling, the

ADS-CCD1201 can be supplied without its internal sample-

Unipolar input range (0 to +10V)

1.2MHz sampling rate

4096-to-1 dynamic range (72.2dB)

Low noise, 400µVrms (1/6 of an LSB)

Outstanding differential nonlinearity error (±0.35 LSB max.)

Small, 24-pin ceramic DDIP

Low power, 1.7 Watts

Operates from ±12V or ±15V supplies

Edge-triggered, no pipeline delay

IN N O VA T IO N a n d E X C E L L E N C E

+10V REFERENCE 21

START CONVERT 16

ANALOG INPUT 20

EOC 15

+5V SUPPLY

S/H

Figure 1. ADS-CCD1201 Functional Block Diagram

CONTROL LOGIC

TIMING AND

NO CONNECT

17, 18

BUFFER

Tel: (508) 339-3000 Fax: (508)339-6356

+12V/+15V SUPPLY

–

FLASH

REF

ADC

hold amplifier. DATEL will also entertain discussions about

including the CDS circuit internal to the ADS-CCD1201. Please

Optimized for CCD Applications

12-Bit, 1.2MHz, Sampling A/D’s

DAC

FUNCTION

BIT 12 (LSB)

BIT 11

BIT 10

BIT 9

BIT 8

BIT7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1 (MSB)

14, 19, 23

GROUND

INPUT/OUTPUT CONNECTIONS

CORRECTION

ADS-CCD1201

–12V/–15V SUPPLY

DIGITAL

LOGIC

For immediate assistance: (800) 233-2765

FUNCTION

–12V/–15V SUPPLY

GROUND

+12V/+15V SUPPLY

+10V REFERENCE OUT

ANALOG INPUT

GROUND

NO CONNECT

START CONVERT

EOC

GROUND

+5V SUPPLY

12 BIT 1 (MSB)

11 BIT 2

10 BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12 (LSB)

Related parts for ADS-CCD1201

ADS-CCD1201 Summary of contents

Page 1

... BIT 6 8 BIT 5 9 BIT 4 10 BIT 3 11 BIT 2 12 BIT 1 (MSB) hold amplifier. DATEL will also entertain discussions about including the CDS circuit internal to the ADS-CCD1201. Please contact us for more details. – S/H DAC + S2 S1 REF FLASH ADC BUFFER TIMING AND ...

Page 2

... S/H Acquisition Time ( to ±0.01%FSR, 10V step) 360 Overvoltage Recovery Time — A/D Conversion Rate 1.2 PHYSICAL/ENVIRONMENTAL UNITS PARAMETERS Volts Operating Temp. Range, Case Volts ADS-CCD1201MC Volts ADS-CCD1201MM +0.3 Volts Thermal Impedance DD Volts jc °C ca Storage Temperature Range Package Type Weight +25° +70°C TYP. MAX. ...

Page 3

... This is the time required before the A/D output data is valid after the analog input is back within the specified range. 3. When operating the ADS-CCD1201 from ±12V supplies, do not drive external circuitry with the REFERENCE OUTPUT (pin 21). The reference’s accuracy and drift specifications may not be met, and loading the circuit may cause accuracy errors within the converter ...

Page 4

... To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit of Figure 2 are guaranteed to compensate for the ADS-CCD1201’s initial accuracy errors and may not be able to compensate for additional system errors. +15V ...

Page 5

... Conversion Time 35ns max. 73ns max. 760ns min. INVALID DATA Figure 4. ADS-CCD1201 Timing Diagram not employ "pipeline" delays to increase its throughput rate. It does not require multiple start convert pulses to bring valid digital data to its output pins. C2 15pF COG R5 ...

Page 6

... Input Frequency (kHz) SNR+D vs. Input Frequency 100 Input Frequency (kHz) Figure 7. Typical ADS-CCD1201 Dynamic Performance vs. Input Frequency at +25°C 120 180 240 300 360 Frequency (kHz) Figure 6. ADS-CCD1201 FFT (f = 480kHz 1.2MHz, V –0.5dB, 16,384 points ...

Page 7

... Figure 8. ADS-CCD1201 Grounded Input Histogram 0 Figure 9. ADS-CCD1201 Histogram and Differential Nonlinearity This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-CCD1201. 4,096 conversions were processed with the input to the ADS-CCD1201 tied to analog ground. ...

Page 8

... TYP. 0.015 (1.524) (0.381) MAX. radius 0.130 TYP. for any pin (3.302) 0.020 0.010 TYP. (0.254) Evaluation Board (without ADS-CCD1201) Heat Sink for ADS-CCD1201 models DS-0274C ® 10/96 ...

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