ADS-112MM-C Murata, ADS-112MM-C Datasheet - Page 3

• Manufacturer Part Number: ADS-112MM-C
• Description: or 0 to +10v input range, no pipeline delay, -55 c to +125 c temperature range, rohs compliant....
• Manufacturer: Murata

TECHNICAL NOTES
1. Applications which are unaffected by endpoint errors or remove them through software will
2. For best performance, always connect the analog and digital ground pins to a ground plane
3. Bypass the analog and digital supplies and the +10V reference (pin 21) to ground with 4.7μF,
4. Obtain straight binary/offset binary output coding by tying COMP BIN (pin 18) to +5V or leaving
DATEL
use the typical connections shown in Figure 3. Remove system errors or adjust the small initial
errors of the ADS-112 to zero using the optional external circuitry shown in Figure 4. The
external adjustment circuit has no effect on the throughput rate.
beneath the converter. The analog and digital grounds are not connected to each other inter-
nally.
25V tantalum electrolytic capacitors in parallel with 0.1μF ceramic capacitors. Bypass the +10V
reference (pin 21) to analog ground (pin 23).
it open. The device has an internal pull-up resistor on this pin. To obtain complementary binary
®
INTERNAL S/H
CONVERT
OUTPUT
START
DATA
EOC
Note: Scale is approximately 50ns per division.
®
N
DATA N-1 VALID
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800ns min.
10ns min.
20ns max.
Conversion Time
20ns max.
150ns, ±25ns
Hold
600ns max.
Figure 2. ADS-112 Timing Diagram
200ns max.
INVALID
Acquisition Time
DATA
250ns
12-Bit, 1MHz, Low-Power Sampling A/D Converters
5. To enable the three-state outputs, connect ENABLE (pin 17) to a logic "0" (low). To disable,
6. Do not change the status of pin 18 when EOC is high.
7. Re-initiating the START CONVERT (pin 16) while EOC is a logic "1" (high) will result in a new
TIMING
or complementary offset binary output coding, tie pin 18 to ground. The pin 18 signal is compat-
ible with CMOS/TTL logic levels for those users desiring dynamic control of this function.
connect pin 17 to a logic "1" (high).
conversion sequence.
Figure 2 shows the relationship between the various input signals. The timing shown applies
over the operating temperature range and over the operating power supply range. These times
are guaranteed by design.
60ns max.
35ns max.
N+1
DATA N VALID
31 Mar 2011 MDA_ADS-112.B02 Page 3 of 6
INVALID
DATA
ADS-112