PL133-37 PhaseLink Corp., PL133-37 Datasheet
PL133-37
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PL133-37 Summary of contents
Page 1
... Reference clock inputs may be LVCMOS or sine-wave signals (the inputs are internally AC-coupled). Offered in a small 3 x 3mm SOT23, the PL133-37 offers the best phase noise and jitter performance and lowest power con- sumption of any comparable IC. CLK1 ...
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... Typical value to use is 0.1 F. Typical CMOS termination 50Ω line Series Resistor 50Ω trace. Typical value 30Ω Tel (408) 517-1668 Fax (408) 517-1688 PL133-37 Description pin(s) to limit noise from the power supply pins should be decoupled separately DD To CMOS Input www.phaselink.com Rev 03/18/11 Page 2 ...
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... No Load Pin Pulled Low, V DD_SB +12mA 3. -12mA 3. 0.4V 2.4V OSD V = 3.3V DD Tel (408) 517-1668 Fax (408) 517-1688 PL133-37 MIN. MAX. V -0 -65 150 S -40 85 MIN. TYP 0 ...
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... Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2880 Zanker Rd., San Jose, California 95134 CONDITIONS V =3.3V, Frequency=26MHz DD Offset=12KHz ~ 5MHz V =3.3V, Frequency=100MHz DD Offset=12KHz ~ 20MHz PL133-37 Additive Phase Jitter: REF Input PL133-37 Output 1000 10000 Offset Frequency (Hz) 2 Tel (408) 517-1668 Fax (408) 517-1688 PL133-37 MIN TYP ...
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... A1 3.00 0.55 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 517-1688 PART NUMBER PL133- None=Tubes R=Tape and Reel Temperature Range C=Commercial (0°C to 70°C) Marking H37 6-Pin SOT23 (Tape and Reel) LLL www.phaselink.com/QA/solderingGreen.pdf Tel (408) 517-1668 Fax (408) 517-1688 ...