IS41LV16256B-35TL-TR ISSI, IS41LV16256B-35TL-TR Datasheet
IS41LV16256B-35TL-TR
Related parts for IS41LV16256B-35TL-TR
IS41LV16256B-35TL-TR Summary of contents
Page 1
... Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41LV16256B ideal for use in 16 and 32-bit wide data bus systems. These features make the IS41LV16256B ideally suited for high band-width graphics, digital signal processing, high- performance computing systems, and peripheral applications ...
Page 2
... IS41LV16256B FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0- CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 262,144 x 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI OE CONTROL LOGIC I/O0-I/O15 Rev ...
Page 3
... IS41LV16256B TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write (1,2) EDO Page-Mode Read (2) 1st Cycle: 2nd Cycle: Any Cycle: EDO Page-Mode Write (1) 1st Cycle: ...
Page 4
... IS41LV16256B Functional Description The IS41LV16256B is a CMOS DRAM optimized for high- speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8 time. The row address is latched by the Row Address Strobe (RAS) ...
Page 5
... IS41LV16256B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage DD I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
Page 6
... IS41LV16256B ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Stand-by Current: TTL Stand-by Current: CMOS Operating Current (2,3,4) Random Read/Write ...
Page 7
... IS41LV16256B AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC Access Time from RAS t RAC Access Time from CAS t CAC t Access Time from Column-Address AA RAS Pulse Width t RAS RAS Precharge Time t RP CAS Pulse Width t (26) ...
Page 8
... IS41LV16256B AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Write Command Pulse Width WP WE Pulse Widths to Disable Outputs t WPZ Write Command to RAS Lead Time t RWL Write Command to CAS Lead Time t CWL t Write Command Setup Time WCS Data-in Hold Time (referenced to RAS) ...
Page 9
... IS41LV16256B Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...
Page 10
... IS41LV16256B READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Note: is referenced from rising edge of RAS or CAS, whichever occurs last OFF RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC Column t RCS t AA ...
Page 11
... IS41LV16256B DON'T CARE) OE EARLY WRITE CYCLE (OE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/28/ RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC CAH t ACH Column t CWL t RWL ...
Page 12
... IS41LV16256B READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I RWC t RAS t CSH t t RCD RAD RAH ASC CAH Column t RWD t t RCS CWD t AWD RAC t CAC t CLZ Open Valid Integrated Silicon Solution, Inc. — ...
Page 13
... IS41LV16256B EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
Page 14
... IS41LV16256B EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I RASP t t CSH RCD CAS, CP CAS CLCH CLCH ACH ACH ASC CAH ASC Column Column t t CWL CWL t t WCS WCS ...
Page 15
... IS41LV16256B EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) RAS t t CRP RCD UCAS/LCAS ASR t RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both 1 ...
Page 16
... IS41LV16256B EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I RASP t CSH CAS CP CAS CAH ASC CAH Column (A) Column ( ...
Page 17
... IS41LV16256B AC WAVEFORMS WE WE READ CYCLE (With WE WE WE-Controlled Disable) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS RAS RAS RAS-ONLY REFRESH CYCLE (OE RAS RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/28/05 t CSH t t RCD CAS ...
Page 18
... IS41LV16256B CBR CBR CBR CBR CBR REFRESH CYCLE (Addresses RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (WE RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. is referenced from rising edge of RAS or CAS, whichever occurs last. ...
Page 19
... ORDERING INFORMATION : 3.3V Commercial Range +70 Speed (ns) Order Part No. 35 IS41LV16256B-35K IS41LV16256B-35KL IS41LV16256B-35T IS41LV16256B-35TL 60 IS41LV16256B-60K IS41LV16256B-60KL IS41LV16256B-60T IS41LV16256B-60TL Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/28/ Package 400-mil SOJ 400-mil SOJ, Lead-free 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free 400-mil SOJ ...
Page 20
... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...
Page 21
... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products ...
Page 22
... D 18.31 18.51 0.721 0.7287 E 10.06 10.26 0.396 0.4040 1 e 0.80 BSC 0.031 BSC E 11.56 11.96 0.455 0.4709 L 0.40 0.60 0.016 0.0236 ISSI should be measured from the bottom of the . c Plastic TSOP (T - Type II) (MS 24) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 44/50 A 1.20 0.0472 A1 0.05 0.15 0.002 0.0059 b 0.30 0.45 0.012 0.0157 c 0 ...