DS1045-5 Maxim Integrated, DS1045-5 Datasheet

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DS1045-5

Manufacturer Part Number
DS1045-5
Description
Delay Lines / Timing Elements
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS1045-5

Function
Active Programmable Delay Line
Package / Case
PDIP-16 Narrow
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
FEATURES
DESCRIPTION
The DS1045 is a programmable silicon delay line having one input and two 4-bit programmable delay
outputs. Each 4-bit programmable output offers the user 16 possible delay values to select from, starting
with a minimum inherent DS1045 delay of 9ns and a maximum achievable delay in the standard DS1045
family of 84ns. The standard DS1045 product line provides the user with three devices having uniform
delay increments of 3ns, 4ns, and 5ns, depending on the device. Table 1 presents standard device family
and delay capability. Additionally, custom delay increments are available for special order through Dallas
Semiconductor.
The DS1045 is TTL and CMOS-compatible and capable of driving ten 74LS-type loads. The output
produced by the DS1045 is both rising and falling edge precise. The DS1045 programmable silicon delay
line has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is
offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC package.
www.maxim-ic.com
All-silicon time delay
Two programmable outputs from a single
input produce output-to-output delays
between 9ns and 84ns depending on device
type
Programmable via four input pins
Programmable increments of 3ns to 5ns with
a minimum of 9ns and a maximum of 84ns
Output pulse is a reproduction of input pulse
after
Delay with both leading and trailing edge
accuracy
Standard 16-pin DIP or surface mount 16-pin
SOIC
Auto-insertable
Low-power CMOS design is TTL-compatible
1 of 6
4-Bit Dual Programmable Delay Line
PIN ASSIGNMENT
PIN DESCRIPTION
IN
OUTA, OUTB
A0-A3
B0-B3
V
GND
EA
CC
GND
See Mech. Drawings
V
EA
DS1045 16-Pin DIP
,
A0
A1
A2
A3
IN
CC
EB
1
2
3
4
5
6
7
8
Section
16
15
14
13
12
11
10
9
V
EB
OUTB
B0
B1
B2
B3
OUTA
CC
DS1045S 16-Pin SOIC (300-mil)
- Delay Line Input
- Delay Line Outputs
- Parallel Program Inputs
- Parallel Program Inputs
- Enable A and B Inputs
- +5V Input
- Ground
GND
for OUT1
for OUT2
V
EA
A0
A1
A2
A3
IN
CC
See Mech. Drawings
1
2
3
4
5
6
7
8
Section
16
15
14
13
12
11
10
9
DS1045
V
EB
OUTB
B0
B1
B2
B3
OUTA
CC
04/26/04

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DS1045-5 Summary of contents

Page 1

... Each 4-bit programmable output offers the user 16 possible delay values to select from, starting with a minimum inherent DS1045 delay of 9ns and a maximum achievable delay in the standard DS1045 family of 84ns. The standard DS1045 product line provides the user with three devices having uniform delay increments of 3ns, 4ns, and 5ns, depending on the device ...

Page 2

... PART NUMBER TABLE Table 1 PART NUMBER STEP ZERO DELAY DS1045-3 DS1045-4 DS1045-5 NOTE: Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for availability. BLOCK DIAGRAM Figure 1 ) requirements, data can be latched on an 8-bit bus. If the enable ...

Page 3

... DELAY VS. PROGRAMMED VALUE Table 2 PART NUMBER DS1045 DS1045 DS1045 PROGRAM VALUES FOR EACH DELAY VALUE DS1045 TEST CIRCUIT Figure 2 TEST SETUP DESCRIPTION Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1045 ...

Page 4

... PHL t 0 PDX t 10 PDV DSE t 0 DHE t EDX t 15 EDV TYP MAX UNITS 5.0 5. +0.5 0.8 A +1.0 A 35 (0°C to 70° MAX UNITS DS1045 NOTES 5%) NOTES 2 ...

Page 5

... Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. TIMING DIAGRAM: NON-LATCHED PARALLEL MODE TIMING DIAGRAM: LATCHED PARALLEL MODE SYMBOL MIN TYP DS1045 (T = 25°C) A MAX UNITS NOTES ...

Page 6

... TIMING DIAGRAM: DS1045 INPUTS TO OUTPUTS TERMINOLOGY PERIOD: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V WI point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V on the leading edge. ...

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