DS1689SN+T&R Maxim Integrated, DS1689SN+T&R Datasheet - Page 20

• Manufacturer Part Number: DS1689SN+T&R
• Description: Real Time Clock
• Manufacturer: Maxim Integrated
• Series: DS1689, DS1693r

Specifications of DS1689SN+T&R

• Rohs: yes
• Function: Clock, Calendar, NV SRAM Control
• Rtc Bus Interface: Multiplexed
• Date Format: DW
• Time Format: HH
• Rtc Memory Size: 114 B
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28

DS1689/DS1693
applied, the on-chip logic always attempts to drive the PWR pin active in response to the enabled
kickstart or wake-up condition. This is true even if PWR was previously inactive as the result of power
being applied by some means other than wake-up or kickstart.
The system can be powered down under software control by setting the PAB bit to logic 1. This causes
the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in
the timing diagram. As V
voltage decays, the IRQ output pin is placed in a high-impedance state when
CC
V
goes below V
. If the system is to be again powered on in response to a wake-up or kickstart, then
CC
PF
both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to setting the
PAB bit.
During interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM
is in effect, PWR and IRQ are tri-stated, and monitoring of wake-up and kickstart takes place.
RAM CLEAR
The DS1689/DS1693 provide a RAM clear function for the 114 bytes of user RAM. When enabled, this
function can be performed regardless of the condition of the V
pin.
CC
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to logic 1, the 114 bytes of user RAM are cleared (all bits set to 1) when an
active-low transition is sensed on the RCLR pin. This action has no effect on either the clock/calendar
settings or upon the contents of the external extended RAM. The RAM clear flag (RF, bank 1, register
04BH) is set when the RAM clear operation has been completed. If V
is present at the time of the RAM
CC
clear and RIE = 1, the IRQ line is also driven low upon completion. The interrupt condition can be
cleared by writing a 0 to the RF bit. The IRQ line then returns to its inactive high level, provided there are
no other pending interrupts. Once the RCLR pin is activated, all read/write accesses are locked out for a
minimum recover time, specified as t
in the Electrical Characteristics section.
REC
When RCE is cleared to 0, the RAM clear function is disabled. The state of the RCLR pin has no effect
on the contents of the user RAM, and transitions on the RCLR pin have no effect on RF.
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