MAX11211EEE+T Maxim Integrated, MAX11211EEE+T Datasheet
MAX11211EEE+T
Specifications of MAX11211EEE+T
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MAX11211EEE+T Summary of contents
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Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO General Description The MAX11209/MAX11211 are ultra-low-power (< 300FA active current), high-resolution, serial-output ADCs. These devices provide the highest resolution per unit power in the industry, and are optimized for ...
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... LINEF = 0, for 1sps to 15sps (Notes AIN buffers disabled = +70NC MIN MAX MIN TYP MAX UNITS 18 Bits 18 2.1 FV RMS 0.55 -15 +15 ppmFSR -15 +15 ppmFSR 50 nV/NC -20 +20 ppmFSR ppmFSR/ 0. 100 90 123 90 dB 144 100 144 dB 100 144 GND AVDD Maxim Integrated ...
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... Input High Voltage Input Hysteresis External Clock LOGIC OUTPUTS (RDY/DOUT, GPIO1–GPIO4) Output Low Level Output High Level Leakage Current Output Capacitance Maxim Integrated MAX11209/MAX11211 - internal clock, single-cycle mode (SCYCLE = 1), T REFP REFN AVDD = +25NC under normal conditions, unless otherwise noted.) ...
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... MIN MAX MIN TYP MAX UNITS 2.7 3.6 V 1.7 3.6 V 235 300 FA 255 0. 185 235 FA 205 0. MHz 200 CNV Maxim Integrated ...
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... AVDD VOLTAGE (V) SLEEP CURRENT vs. TEMPERATURE 1.0 0.8 0.6 TOTAL 0.4 DVDD 0.2 AVDD 0 -45 - TEMPERATURE (°C) Maxim Integrated MAX11209/MAX11211 Typical Operating Characteristics - V = 2.5V; internal clock REFN A ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (SIGNAL OR REFERENCE BUFFERS ENABLED) 260 240 T = +85°C A 220 T = +25°C A 200 ...
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... INPUT VOLTAGE (V) PSRR vs. FREQUENCY (DATA RATE 120sps) 0 -20 -40 -60 -80 AVDD -100 DVDD -120 -140 1 10 100 1000 10,000 FREQUENCY (Hz) CMRR vs. FREQUENCY 0 -20 -40 -60 -80 120sps -100 -120 10sps -140 1 10 100 1000 10,000 FREQUENCY (Hz) = +85° -45°C A 0.5 1.0 1.5 2.0 2.5 100,000 100,000 Maxim Integrated ...
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... Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO AVDD DVDD GND AINP AINN REFP REFN *PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11209. Maxim Integrated MAX11209/MAX11211 TIMING DIGITAL FILTER 4 (SINC ) 3RD-ORDER DELTA-SIGMA MODULATOR MAX11209* MAX11211 Functional Diagram CLOCK GENERATOR DIGITAL LOGIC ...
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... GPIO4 General-Purpose I/O 4. Register controllable using SPI. 8 TOP VIEW + GPIO1 1 16 GPIO2 2 15 MAX11209 GPIO3 3 14 MAX11211 GND 4 13 REFP 5 12 REFN 6 11 AINN 7 10 AINP 8 9 QSOP FUNCTION Pin Configuration GPIO4 CLK SCLK RDY/DOUT DIN CS DVDD AVDD Pin Description Maxim Integrated ...
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... LINEF bit = 1 sets the clock frequency to 2.048MHz and the input sampling frequency to 204.8kHz. Maxim Integrated MAX11209/MAX11211 the inputs from the capacitive load presented by the modulator, allowing for high source-impedance analog transducers ...
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... The system full-scale calibration requires 100ms to complete, and the SGC register con- tains values that correct for the chip full-scale value. See Tables 3a and 3b for an example of a self-calibration sequence and a system calibration sequence. /4. The range of digital gain correc- REF Maxim Integrated ...
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... The devices include a SINC 4 digital filter that produces spectral nulls at the multiples of the data rate. For all data rates less than 30sps, a spectral null occurs at the Maxim Integrated MAX11209/MAX11211 REGISTER SCOC SCGC SOC 0x000000 ...
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... DATA RATE 100.000sps 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 200 400 600 800 1000 1200 1400 1600 1800 FREQUENCY (Hz DIO4 DIO3 DIO2 DIO4 DIO3 DIO2 2000 2000 B0 DIO1 1 B0 DIO1 0 Maxim Integrated ...
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... VALUE 18-BIT OUTPUT DATA CYCLE MSB Figure 4. MAX11209 Digital Programmable Gain Example (10sps Output Rate) Maxim Integrated MAX11209/MAX11211 It is not always necessary to transition to a high-imped- ance state between channel selections, but depends on the source analog signals as well as the control structure of the multiplexed switches. ...
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... SPI timing diagrams CAL1 CAL0 IMPD RS3 RS2 RS1 RS0 W CSH1 CSW t CSS1 8 RATE2 RATE1 RATE0 t DOD HIGH-Z t CSW t CSH1 t CSS1 DOD HIGH-Z Maxim Integrated ...
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... B7 B6 BIT NAME START = 1 MODE = 0 Table 6. Command Byte (MODE = 1) BIT B7 B6 BIT NAME START = 1 MODE = 1 Note: The START bit is used to synchronize the data from the host device. The START bit is always 1. Maxim Integrated MAX11209/MAX11211 DOT RS3 RS2 ...
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... REGISTER SIZE (BITS) 0x00 0x02 0x0F 0x1E 0x000000 0x000000 0x000000 0x000000 0x000000 RATE1 RATE0 Maxim Integrated ...
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... SOC 0x5 R/W SGC 0x6 R/W SCOC 0x7 R/W SCGC R/W 0x8 *These DGAIN_ bits set the digital gain for the MAX11209 These bits are don’t-care bits for the MAX11211. Maxim Integrated MAX11209/MAX11211 SYSOR RATE2 RATE1 LINEF EXTCLK U/B DIR4 DIR3 DIR2 ...
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... RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the DATA read operation has completed RATE2 RATE1 RATE0 STAT1: Status Register MSTAT Maxim Integrated B0 RDY 0 ...
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... RDY/DOUT from must be used to synchronize the DATA register read back. If the RDY/DOUT output is not used to synchronize the DATA read back, a timing hazard exists where the DATA register is updated internally after a conversion has completed simultaneously with the DATA register being read out, causing an incorrect read of DATA. Maxim Integrated MAX11209/MAX11211 B6 ...
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... this location enables the use of the self-calibration offset value when computing the final offset and gain corrected data value DIR3 DIR2 DIR1 DGAIN1* DGAIN0* NOSYSG CTRL2: Control 2 Register DIO4 DIO3 DIO2 CTRL3: Control 3 Register NOSYSO NOSCG NOSCO Maxim Integrated B0 DIO1 1 B0 RESERVED 0 /gain REF ...
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... Table 16a. Output Data Format for the Unipolar Input Range INPUT VOLTAGE AINP ≥ V REF V × 1 − REF REF 18 − Maxim Integrated ). = 0V), and the positive full scale is 0x1FFFF (V AINN D16 D15 D14 AINN ...
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... B21 B20 B13 B12 TWO’S COMPLEMENT FORMAT 0x1FFFF 0x1FFFE 0x00001 0x00000 0x3FFFF 0x20001 0x20000 B19 B18 B17 B11 B10 B16 Maxim Integrated ...
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... The self-calibration offset value is also applied prior to the 2x scale factor associated with unipolar mode. Table 19. SCOC Register (Read/Write) BIT B23 0 DEFAULT BIT B15 DEFAULT 0 BIT B7 DEFAULT 0 Maxim Integrated B22 B21 B20 B14 B13 B12 ...
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... SCGC: Self-Calibration Gain Register B19 B18 B17 B11 B10 CONTINUOUS DATA RATE (sps) — — — — 60 120 240 480 CONTINUOUS DATA RATE (sps) — — — — 50 100 200 400 Maxim Integrated B16 ...
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... REFP REFN AINP AINN Figure 9. Resistive Bridge Measurement Circuit Maxim Integrated MAX11209/MAX11211 See Figure 8 for the RTD temperature measurement circuit and Figure 9 for a resistive bridge measurement circuit. Adding more active circuitry to the analog input signal path is not always the best solution to a small-signal problem ...
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... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE 16 QSOP MAX11209 Chip Information Package Information PACKAGE OUTLINE TYPE CODE NO. E16+4 21-0055 LAND PATTERN NO. 90-0167 Maxim Integrated ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...